mux2_1.vhd

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2_1 IS
PORT(X1,X2:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
	 SEL:IN STD_LOGIC;
	 Q: OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
END MUX2_1;
ARCHITECTURE ART OF MUX2_1 IS
BEGIN
	PROCESS(SEL,X1,X2)
	BEGIN
            IF SEL='0' THEN
                Q<=X1;
            ELSE
	            Q<=X2;
	        END IF;
	END PROCESS;
END ART;