generator_reg81.vhd

来自「数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过」· VHDL 代码 · 共 44 行

------------------------------------------------------------------------------------
-- DESCRIPTION   :  Flip-flop D type
--                  Width: 8
--                  Clock active: high
--                  Asynchronous clear active: high
--                  Clock enable active: high
-- 
------------------------------------------------------------------------------------



library IEEE;
use IEEE.std_logic_1164.all;

entity generator_reg81 is
	port (
		CLR : in std_logic;
		CLKK : in std_logic;
		DATA : in std_logic_vector (9 downto 0);
		Q1 : out std_logic_vector (9 downto 0)
	);
end entity;



architecture reg_arch8 of generator_reg81 is
signal TEMP_Q_1: std_logic_vector (9 downto 0);
begin

	process (CLKK, CLR)
	begin

		if CLR = '1' then
			TEMP_Q_1 <= (others => '0');
		elsif rising_edge(CLKK) then
				TEMP_Q_1 <= DATA;
		end if;

	end process;

	Q1 <= TEMP_Q_1;

end architecture;