generator_accb.vhd

来自「数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过」· VHDL 代码 · 共 68 行

------------------------------------------------------------------------------------
-- DESCRIPTION   :  Cascadable Accumulator with Adder
--                  Width : 6
--                  CLK (CLK) active : high
--                  CLR (CLR) active : high
--                  CLR (CLR) type : asynchronous
--                  CE (CE) active : high
--
------------------------------------------------------------------------------------



library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity generator_accB is
	port (
		CLK : in std_logic;
	    CLR : in std_logic;
		A : in std_logic_vector (21 downto 0);
		START: OUT STD_LOGIC;
		SEL: OUT STD_LOGIC;
		Q : out std_logic_vector (7 downto 0)
	);
end entity;



architecture acc_arch of generator_accB is
signal REG_Q  : std_logic_vector (21 downto 0);
signal TEMP_Q : std_logic_vector (21 downto 0);
SIGNAL TEMP : STD_LOGIC;
begin
	process (REG_Q,A)
	begin
		TEMP_Q <= REG_Q + A;
	end process;

	process(CLK,CLR,TEMP_Q)
	begin
		if CLR = '1' then
			REG_Q <= "0000000000000000000000";
		ELSif rising_edge(CLK) then
             IF TEMP_Q >= "1100100000000000000000" THEN
                REG_Q<="0000000000000000000000";
                START<='1';
                TEMP<=NOT TEMP;
          	 ELSE	REG_Q <= TEMP_Q;
                    START<='0';
             END IF;

		end if;
	end process;
	SEL<=TEMP;
--	PROCESS(TEMP_Q)
--    BEGIN
--        IF TEMP_Q(21 DOWNTO 14)="11000111" THEN
--           START<='1';
--        ELSIF TEMP_Q(21 DOWNTO 14)="00000000" THEN
--            START<='0';
--        END IF;    
--    END PROCESS;

    Q<=REG_Q(21 DOWNTO 14);

end architecture;