test.fit.qmsg

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "1 " "Info: Fitter routing operations ending: elapsed time = 1 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "6 " "Warning: Following 6 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "XFER GND " "Info: Pin XFER has GND driving its datain port" {  } { { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 688 1000 1176 704 "XFER" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "XFER" } } } } { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "" { XFER } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/TEST.fld" "" "" { Floorplan "e:/ywh/quartusii/scanwave/TEST.fld" "" "" { XFER } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "A1 GND " "Info: Pin A1 has GND driving its datain port" {  } { { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 624 1000 1176 640 "A1" ""