fredevider2.vhd

来自「数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过」· VHDL 代码 · 共 21 行

--  偶数分频器,分频比为2(N+1)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FREDEVIDER2 IS
PORT
   (CLKIN:IN STD_LOGIC;
    CLKOUT:OUT STD_LOGIC);
END;

ARCHITECTURE ART OF FREDEVIDER2 IS
SIGNAL CLK:STD_LOGIC;
BEGIN 
    PROCESS(CLKIN)
   BEGIN
      IF RISING_EDGE(CLKIN) THEN
            CLK<=NOT CLK;
      END IF;
   END PROCESS;
 CLKOUT<=CLK;
END;