fredevider8.vhd

来自「数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过」· VHDL 代码 · 共 28 行

--  偶数分频器,分频比为2(N+1)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FREDEVIDER8 IS
PORT
   (CLKIN:IN STD_LOGIC;
    CLKOUT:OUT STD_LOGIC);
END;

ARCHITECTURE ART OF FREDEVIDER8 IS
CONSTANT N:INTEGER:=5;                --定义常数N,默认参数为3，即8分频
SIGNAL COUNTER:INTEGER RANGE 0 TO N;  --引用常数N
SIGNAL CLK:STD_LOGIC;
BEGIN 
    PROCESS(CLKIN)
   BEGIN
      IF RISING_EDGE(CLKIN) THEN
         IF COUNTER=N THEN            --第二次引用常数N
            COUNTER<=0;
            CLK<=NOT CLK;
         ELSE
            COUNTER<=COUNTER+1;
         END IF;
      END IF;
   END PROCESS;
 CLKOUT<=CLK;
END;