freq_count.vhd

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY FREQ_COUNT IS
PORT
   (CLK:IN STD_LOGIC;
    CLK2: IN STD_LOGIC;
    CLR: IN STD_LOGIC;
    QH,QL:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END;

ARCHITECTURE ART OF FREQ_COUNT IS

SIGNAL FULL:STD_LOGIC;
SIGNAL TEMP: STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN 
    PROCESS(CLK,CLR)
VARIABLE COUNT1:INTEGER RANGE 0 TO 50000;
    BEGIN
    IF CLR='1' THEN
        COUNT1:=0;
        FULL<='0';
   ELSIF CLK 'EVENT AND CLK='1' THEN 
       IF COUNT1>49999 THEN 
            FULL<='1';
            COUNT1:=50000;
       ELSE
            COUNT1:=COUNT1+1;
       END IF;
    END IF;
    END PROCESS;

    PROCESS(CLK2,CLR,FULL)
VARIABLE COUNT2:INTEGER RANGE 0 TO 65536;
    BEGIN
    IF CLR='1' THEN
        COUNT2:=0;
    ELSIF CLK2 'EVENT AND CLK2='1' THEN
        IF FULL='1' THEN
            TEMP<=CONV_STD_LOGIC_VECTOR(COUNT2,16); 
        ELSE
            COUNT2:=COUNT2+1;
        END IF;
    END IF;
    END PROCESS;
    
    QL<=TEMP(7 DOWNTO 0);
    QH<=TEMP(15 DOWNTO 8);
END;