mux2.vhd

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2 IS
PORT(RDR,WRR,RDW,WRW:IN STD_LOGIC;
	CLK,SEL:IN STD_LOGIC;
    RDN,WRN,GX2:OUT STD_LOGIC);
END MUX2;
ARCHITECTURE ART OF MUX2 IS
BEGIN
	PROCESS(CLK,SEL)
	BEGIN
		IF CLK'EVENT AND CLK='1'THEN
          IF SEL='0' THEN
            RDN<=RDW;
            WRN<=WRW;
            GX2<='1';
	      ELSE RDN<=RDR;
            WRN<=WRR;
            GX2<='0';
          END IF;
		END IF;
	END PROCESS;
END ART;