mux2_2.vhd

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2_2 IS
PORT(X1,X2:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	 SEL:IN STD_LOGIC;
	 SEL_A,SEL_B:IN STD_LOGIC;
	 Q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END MUX2_2;
ARCHITECTURE ART OF MUX2_2 IS
BEGIN
	PROCESS(SEL_A,SEL_B,SEL)
	BEGIN
	    IF SEL_A='1' AND SEL_B='1' THEN
            IF SEL='0' THEN
                Q<=X1;
            ELSE
	            Q<=X2;
	        END IF;
	    ELSIF SEL_A='1' AND SEL_B='0' THEN
	        Q<=X2;
	    ELSIF SEL_A='0' AND SEL_B='1' THEN
	        Q<=X1;
	    ELSE Q<=X2;
	    END IF;
	END PROCESS;
END ART;