triwave.vhd

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY TRIWAVE IS
PORT(CLK:IN STD_LOGIC;
	DOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END TRIWAVE;
ARCHITECTURE ART OF TRIWAVE IS
SIGNAL Q:STD_LOGIC;
BEGIN 
	PROCESS(CLK)
    variable D: INTEGER RANGE 0 TO 199;
	BEGIN
		IF CLK'EVENT AND CLK='1' THEN
			D:=D+1;
		END IF;
	DOUT<=CONV_STD_LOGIC_VECTOR(D,8);
	END PROCESS;
END ART;