scanwave.map.eqn

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

--N1_RD is MAX114:inst11|RD
--operation mode is normal

N1_RD_lut_out = !N1_cnt[1] & !N1_cnt[2] & !N1_cnt[0];
N1_RD = DFFEA(N1_RD_lut_out, CLK, VCC, , N1L82, , );


--N1_B is MAX114:inst11|B
--operation mode is normal

N1_B_lut_out = N1_cnt[1] & N1_cnt[3] & !N1_cnt[2] & !N1_cnt[0];
N1_B = DFFEA(N1_B_lut_out, CLK, VCC, , N1L92, , );


--B1_TEMP_Q_1[7] is generator_reg81:79|TEMP_Q_1[7]
--operation mode is normal

B1_TEMP_Q_1[7]_lut_out = G1_REG_Q[21];
B1_TEMP_Q_1[7] = DFFEA(B1_TEMP_Q_1[7]_lut_out, K1_CLK, !H1_TMP, , , , );


--B1_TEMP_Q_1[6] is generator_reg81:79|TEMP_Q_1[6]
--operation mode is normal

B1_TEMP_Q_1[6]_lut_out = G1_REG_Q[20];
B1_TEMP_Q_1[6] = DFFEA(B1_TEMP_Q_1[6]_lut_out, K1_CLK, !H1_TMP, , , , );


--B1_TEMP_Q_1[5] is generator_reg81:79|TEMP_Q_1[5]
--operation mode is normal

B1_TEMP_Q_1[5]_lut_out = G1_REG_Q[19];
B1_TEMP_Q_1[5] = DFFEA(B1_TEMP_Q_1[5]_lut_out, K1_CLK, !H1_TMP, , , , );


--B1_TEMP_Q_1[4] is generator_reg81:79|TEMP_Q_1[4]
--operation mode is normal

B1_TEMP_Q_1[4]_lut_out = G1_REG_Q[18];
B1_TEMP_Q_1[4] = DFFEA(B1_TEMP_Q_1[4]_lut_out, K1_CLK, !H1_TMP, , , , );


--B1_TEMP_Q_1[3] is generator_reg81:79|TEMP_Q_1[3]
--operation mode is normal

B1_TEMP_Q_1[3]_lut_out = G1_REG_Q[17];
B1_TEMP_Q_1[3] = DFFEA(B1_TEMP_Q_1[3]_lut_out, K1_CLK, !H1_TMP, , , , );


--B1_TEMP_Q_1[2] is generator_reg81:79|TEMP_Q_1[2]
--operation mode is normal

B1_TEMP_Q_1[2]_lut_out = G1_REG_Q[16];
B1_TEMP_Q_1[2] = DFFEA(B1_TEMP_Q_1[2]_lut_out, K1_CLK, !H1_TMP, , , , );


--B1_TEMP_Q_1[1] is generator_reg81:79|TEMP_Q_1[1]
--operation mode is normal

B1_TEMP_Q_1[1]_lut_out = G1_REG_Q[15];
B1_TEMP_Q_1[1] = DFFEA(B1_TEMP_Q_1[1]_lut_out, K1_CLK, !H1_TMP, , , , );


--B1_TEMP_Q_1[0] is generator_reg81:79|TEMP_Q_1[0]
--operation mode is normal

B1_TEMP_Q_1[0]_lut_out = G1_REG_Q[14];
B1_TEMP_Q_1[0] = DFFEA(B1_TEMP_Q_1[0]_lut_out, K1_CLK, !H1_TMP, , , , );


--L1_TEMP[7] is VOLTAGE_CONV:inst9|TEMP[7]
--operation mode is normal

L1_TEMP[7]_lut_out = L1L51;
L1_TEMP[7] = DFFEA(L1_TEMP[7]_lut_out, !P1_CLK, !S1_EN, , !L1L03, , );


--L2_TEMP[7] is VOLTAGE_CONV:inst17|TEMP[7]
--operation mode is normal

L2_TEMP[7]_lut_out = L2L51;
L2_TEMP[7] = DFFEA(L2_TEMP[7]_lut_out, !P1_CLK, !S1_EN, , !L2L03, , );


--H1_RAMTMP0[0] is BUS_1:inst5|RAMTMP0[0]
--operation mode is normal

H1_RAMTMP0[0]_lut_out = H1_RAMTMP0[0] & (X1_q_a[1] # A1L55 & H1L49) # !H1_RAMTMP0[0] & A1L55 & H1L49;
H1_RAMTMP0[0] = DFFEA(H1_RAMTMP0[0]_lut_out, !CLK, VCC, , H1L92, , );


--G1_TEMP is generator_accB:inst4|TEMP
--operation mode is normal

G1_TEMP_lut_out = !G1_TEMP;
G1_TEMP = DFFEA(G1_TEMP_lut_out, K1_CLK, VCC, , G1L07, , );


--H1_RAMTMP0[1] is BUS_1:inst5|RAMTMP0[1]
--operation mode is normal

H1_RAMTMP0[1]_lut_out = H1_RAMTMP0[1] & (X1_q_a[1] # A1L45 & H1L49) # !H1_RAMTMP0[1] & A1L45 & H1L49;
H1_RAMTMP0[1] = DFFEA(H1_RAMTMP0[1]_lut_out, !CLK, VCC, , H1L92, , );


--F1L8 is MUX2_3:inst3|Q[7]~516
--operation mode is normal

F1L8 = H1_RAMTMP0[0] & (G1_TEMP # !H1_RAMTMP0[1]);


--F1L9 is MUX2_3:inst3|Q[7]~517
--operation mode is normal

F1L9 = L1_TEMP[7] & (L2_TEMP[7] # F1L8) # !L1_TEMP[7] & L2_TEMP[7] & !F1L8;


--L1_TEMP[6] is VOLTAGE_CONV:inst9|TEMP[6]
--operation mode is normal

L1_TEMP[6]_lut_out = L1L31;
L1_TEMP[6] = DFFEA(L1_TEMP[6]_lut_out, !P1_CLK, !S1_EN, , !L1L03, , );


--L2_TEMP[6] is VOLTAGE_CONV:inst17|TEMP[6]
--operation mode is normal

L2_TEMP[6]_lut_out = L2L31;
L2_TEMP[6] = DFFEA(L2_TEMP[6]_lut_out, !P1_CLK, !S1_EN, , !L2L03, , );


--F1L7 is MUX2_3:inst3|Q[6]~518
--operation mode is normal

F1L7 = L1_TEMP[6] & (L2_TEMP[6] # F1L8) # !L1_TEMP[6] & L2_TEMP[6] & !F1L8;


--L1_TEMP[5] is VOLTAGE_CONV:inst9|TEMP[5]
--operation mode is normal

L1_TEMP[5]_lut_out = L1L11;
L1_TEMP[5] = DFFEA(L1_TEMP[5]_lut_out, !P1_CLK, !S1_EN, , !L1L03, , );


--L2_TEMP[5] is VOLTAGE_CONV:inst17|TEMP[5]
--operation mode is normal

L2_TEMP[5]_lut_out = L2L11;
L2_TEMP[5] = DFFEA(L2_TEMP[5]_lut_out, !P1_CLK, !S1_EN, , !L2L03, , );


--F1L6 is MUX2_3:inst3|Q[5]~519
--operation mode is normal

F1L6 = L1_TEMP[5] & (L2_TEMP[5] # F1L8) # !L1_TEMP[5] & L2_TEMP[5] & !F1L8;


--L1_TEMP[4] is VOLTAGE_CONV:inst9|TEMP[4]
--operation mode is normal

L1_TEMP[4]_lut_out = L1L9;
L1_TEMP[4] = DFFEA(L1_TEMP[4]_lut_out, !P1_CLK, !S1_EN, , !L1L03, , );


--L2_TEMP[4] is VOLTAGE_CONV:inst17|TEMP[4]
--operation mode is normal

L2_TEMP[4]_lut_out = L2L9;
L2_TEMP[4] = DFFEA(L2_TEMP[4]_lut_out, !P1_CLK, !S1_EN, , !L2L03, , );


--F1L5 is MUX2_3:inst3|Q[4]~520
--operation mode is normal

F1L5 = L1_TEMP[4] & (L2_TEMP[4] # F1L8) # !L1_TEMP[4] & L2_TEMP[4] & !F1L8;


--L1_TEMP[3] is VOLTAGE_CONV:inst9|TEMP[3]
--operation mode is normal

L1_TEMP[3]_lut_out = L1L7;
L1_TEMP[3] = DFFEA(L1_TEMP[3]_lut_out, !P1_CLK, !S1_EN, , !L1L03, , );


--L2_TEMP[3] is VOLTAGE_CONV:inst17|TEMP[3]
--operation mode is normal

L2_TEMP[3]_lut_out = L2L7;
L2_TEMP[3] = DFFEA(L2_TEMP[3]_lut_out, !P1_CLK, !S1_EN, , !L2L03, , );


--F1L4 is MUX2_3:inst3|Q[3]~521
--operation mode is normal

F1L4 = L1_TEMP[3] & (L2_TEMP[3] # F1L8) # !L1_TEMP[3] & L2_TEMP[3] & !F1L8;


--L1_TEMP[2] is VOLTAGE_CONV:inst9|TEMP[2]
--operation mode is normal

L1_TEMP[2]_lut_out = L1L5;
L1_TEMP[2] = DFFEA(L1_TEMP[2]_lut_out, !P1_CLK, !S1_EN, , !L1L03, , );


--L2_TEMP[2] is VOLTAGE_CONV:inst17|TEMP[2]
--operation mode is normal

L2_TEMP[2]_lut_out = L2L5;
L2_TEMP[2] = DFFEA(L2_TEMP[2]_lut_out, !P1_CLK, !S1_EN, , !L2L03, , );


--F1L3 is MUX2_3:inst3|Q[2]~522
--operation mode is normal

F1L3 = L1_TEMP[2] & (L2_TEMP[2] # F1L8) # !L1_TEMP[2] & L2_TEMP[2] & !F1L8;


--L1_TEMP[1] is VOLTAGE_CONV:inst9|TEMP[1]
--operation mode is normal

L1_TEMP[1]_lut_out = L1L3;
L1_TEMP[1] = DFFEA(L1_TEMP[1]_lut_out, !P1_CLK, !S1_EN, , !L1L03, , );


--L2_TEMP[1] is VOLTAGE_CONV:inst17|TEMP[1]
--operation mode is normal

L2_TEMP[1]_lut_out = L2L3;
L2_TEMP[1] = DFFEA(L2_TEMP[1]_lut_out, !P1_CLK, !S1_EN, , !L2L03, , );


--F1L2 is MUX2_3:inst3|Q[1]~523
--operation mode is normal

F1L2 = L1_TEMP[1] & (L2_TEMP[1] # F1L8) # !L1_TEMP[1] & L2_TEMP[1] & !F1L8;


--L1_TEMP[0] is VOLTAGE_CONV:inst9|TEMP[0]
--operation mode is normal

L1_TEMP[0]_lut_out = L1L1;
L1_TEMP[0] = DFFEA(L1_TEMP[0]_lut_out, !P1_CLK, !S1_EN, , !L1L03, , );


--L2_TEMP[0] is VOLTAGE_CONV:inst17|TEMP[0]
--operation mode is normal

L2_TEMP[0]_lut_out = L2L1;
L2_TEMP[0] = DFFEA(L2_TEMP[0]_lut_out, !P1_CLK, !S1_EN, , !L2L03, , );


--F1L1 is MUX2_3:inst3|Q[0]~524
--operation mode is normal

F1L1 = L1_TEMP[0] & (L2_TEMP[0] # F1L8) # !L1_TEMP[0] & L2_TEMP[0] & !F1L8;


--N1_cnt[1] is MAX114:inst11|cnt[1]
--operation mode is normal

N1_cnt[1]_lut_out = N1_cnt[1] & !N1_cnt[0] # !N1_cnt[1] & N1_cnt[0] & (N1_cnt[2] # INTN);
N1_cnt[1] = DFFEA(N1_cnt[1]_lut_out, CLK, VCC, , , , );


--N1_cnt[2] is MAX114:inst11|cnt[2]
--operation mode is normal

N1_cnt[2]_lut_out = !N1_cnt[2];
N1_cnt[2] = DFFEA(N1_cnt[2]_lut_out, CLK, VCC, , N1L1, , );


--N1_cnt[0] is MAX114:inst11|cnt[0]
--operation mode is normal

N1_cnt[0]_lut_out = N1_cnt[0] & !N1_cnt[1] & !INTN & !N1_cnt[2] # !N1_cnt[0] & (N1_cnt[2] # !INTN # !N1_cnt[1]);
N1_cnt[0] = DFFEA(N1_cnt[0]_lut_out, CLK, VCC, , , , );


--N1L82 is MAX114:inst11|Mux~318
--operation mode is normal

N1L82 = !N1_cnt[2] & !N1_cnt[0];


--N1_cnt[3] is MAX114:inst11|cnt[3]
--operation mode is normal

N1_cnt[3]_lut_out = !N1_cnt[3];
N1_cnt[3] = DFFEA(N1_cnt[3]_lut_out, CLK, VCC, , N1L03, , );


--N1L92 is MAX114:inst11|Mux~319
--operation mode is normal

N1L92 = N1_cnt[1] & !N1_cnt[2] & !N1_cnt[0];


--G1_REG_Q[21] is generator_accB:inst4|REG_Q[21]
--operation mode is normal

G1_REG_Q[21]_lut_out = G1L34 & (G1L76 # !G1L14);
G1_REG_Q[21] = DFFEA(G1_REG_Q[21]_lut_out, K1_CLK, !H1_TMP, , , , );


--K1_CLK is FREDEVIDER8:inst8|CLK
--operation mode is normal

K1_CLK_lut_out = !K1_CLK;
K1_CLK = DFFEA(K1_CLK_lut_out, CLK, VCC, , K1L6, , );


--H1_TMP is BUS_1:inst5|TMP
--operation mode is normal

H1_TMP_lut_out = H1_TMP & (X1_q_a[0] # H1_LATCH_ADDRES[1] & H1L101) # !H1_TMP & H1_LATCH_ADDRES[1] & H1L101;
H1_TMP = DFFEA(H1_TMP_lut_out, !CLK, VCC, , H1L92, , );


--G1_REG_Q[20] is generator_accB:inst4|REG_Q[20]
--operation mode is normal

G1_REG_Q[20]_lut_out = G1L14 & (G1L76 # !G1L34);
G1_REG_Q[20] = DFFEA(G1_REG_Q[20]_lut_out, K1_CLK, !H1_TMP, , , , );


--G1_REG_Q[19] is generator_accB:inst4|REG_Q[19]
--operation mode is normal

G1_REG_Q[19]_lut_out = G1L93 & (G1L76 # !G1L34 # !G1L14);
G1_REG_Q[19] = DFFEA(G1_REG_Q[19]_lut_out, K1_CLK, !H1_TMP, , , , );


--G1_REG_Q[18] is generator_accB:inst4|REG_Q[18]
--operation mode is normal