scanwave.map.summary

来自「数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Tue Aug 28 09:56:26 2007
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Web Edition
Revision Name : scanwave
Top-level Entity Name : SCANWAVE
Family : Cyclone
Total logic elements : 518
Total pins : 53
Total virtual pins : 0
Total memory bits : 32,768
Total PLLs : 0