qiangdaqi.tan.qmsg

用verilog实现的抢答器程序,在Quartus II上编译通过并成功运行

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "S3 register register Q\[3\] Q\[3\] 420.17 MHz Internal " "Info: Clock \"S3\" Internal fmax is restricted to 420.17 MHz between source register \"Q\[3\]\" and destination register \"Q\[3\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.742 ns + Longest register register " "Info: + Longest register to register delay is 1.742 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q\[3\] 1 REG LCFF_X32_Y3_N15 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y3_N15; Fanout = 6; REG Node = 'Q\[3\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q[3] } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.496 ns) + CELL(0.150 ns) 0.646 ns WideNor0~11 2 COMB LCCOMB_X33_Y3_N12 3 " "Info: 2: + IC(0.496 ns) + CELL(0.150 ns) = 0.646 ns; Loc. = LCCOMB_X33_Y3_N12; Fanout = 3; COMB Node = 'WideNor0~11'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "0.646 ns" { Q[3] WideNor0~11 } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(0.660 ns) 1.742 ns Q\[3\] 3 REG LCFF_X32_Y3_N15 6 " "Info: 3: + IC(0.436 ns) + CELL(0.660 ns) = 1.742 ns; Loc. = LCFF_X32_Y3_N15; Fanout = 6; REG Node = 'Q\[3\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.096 ns" { WideNor0~11 Q[3] } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.810 ns ( 46.50 % ) " "Info: Total cell delay = 0.810 ns ( 46.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.932 ns ( 53.50 % ) " "Info: Total interconnect delay = 0.932 ns ( 53.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.742 ns" { Q[3] WideNor0~11 Q[3] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "1.742 ns" { Q[3] WideNor0~11 Q[3] } { 0.000ns 0.496ns 0.436ns } { 0.000ns 0.150ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "S3 destination 2.296 ns + Shortest register " "Info: + Shortest clock path from clock \"S3\" to destination register is 2.296 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns S3 1 CLK PIN_AE14 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_AE14; Fanout = 1; CLK Node = 'S3'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { S3 } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.760 ns) + CELL(0.537 ns) 2.296 ns Q\[3\] 2 REG LCFF_X32_Y3_N15 6 " "Info: 2: + IC(0.760 ns) + CELL(0.537 ns) = 2.296 ns; Loc. = LCFF_X32_Y3_N15; Fanout = 6; REG Node = 'Q\[3\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.297 ns" { S3 Q[3] } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 66.90 % ) " "Info: Total cell delay = 1.536 ns ( 66.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.760 ns ( 33.10 % ) " "Info: Total interconnect delay = 0.760 ns ( 33.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "2.296 ns" { S3 Q[3] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "2.296 ns" { S3 S3~combout Q[3] } { 0.000ns 0.000ns 0.760ns } { 0.000ns 0.999ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "S3 source 2.296 ns - Longest register " "Info: - Longest clock path from clock \"S3\" to source register is 2.296 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns S3 1 CLK PIN_AE14 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_AE14; Fanout = 1; CLK Node = 'S3'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { S3 } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.760 ns) + CELL(0.537 ns) 2.296 ns Q\[3\] 2 REG LCFF_X32_Y3_N15 6 " "Info: 2: + IC(0.760 ns) + CELL(0.537 ns) = 2.296 ns; Loc. = LCFF_X32_Y3_N15; Fanout = 6; REG Node = 'Q\[3\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.297 ns" { S3 Q[3] } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 66.90 % ) " "Info: Total cell delay = 1.536 ns ( 66.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.760 ns ( 33.10 % ) " "Info: Total interconnect delay = 0.760 ns ( 33.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "2.296 ns" { S3 Q[3] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "2.296 ns" { S3 S3~combout Q[3] } { 0.000ns 0.000ns 0.760ns } { 0.000ns 0.999ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "2.296 ns" { S3 Q[3] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "2.296 ns" { S3 S3~combout Q[3] } { 0.000ns 0.000ns 0.760ns } { 0.000ns 0.999ns 0.537ns } "" } } { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "2.296 ns" { S3 Q[3] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "2.296 ns" { S3 S3~combout Q[3] } { 0.000ns 0.000ns 0.760ns } { 0.000ns 0.999ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.742 ns" { Q[3] WideNor0~11 Q[3] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "1.742 ns" { Q[3] WideNor0~11 Q[3] } { 0.000ns 0.496ns 0.436ns } { 0.000ns 0.150ns 0.660ns } "" } } { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "2.296 ns" { S3 Q[3] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "2.296 ns" { S3 S3~combout Q[3] } { 0.000ns 0.000ns 0.760ns } { 0.000ns 0.999ns 0.537ns } "" } } { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "2.296 ns" { S3 Q[3] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "2.296 ns" { S3 S3~combout Q[3] } { 0.000ns 0.000ns 0.760ns } { 0.000ns 0.999ns 0.537ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q[3] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "" { Q[3] } {  } {  } "" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 22 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "Q\[3\] K S3 2.383 ns register " "Info: tsu for register \"Q\[3\]\" (data pin = \"K\", clock pin = \"S3\") is 2.383 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.715 ns + Longest pin register " "Info: + Longest pin to register delay is 4.715 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns K 1 PIN PIN_N25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N25; Fanout = 2; PIN Node = 'K'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { K } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.182 ns) + CELL(0.438 ns) 3.619 ns WideNor0~11 2 COMB LCCOMB_X33_Y3_N12 3 " "Info: 2: + IC(2.182 ns) + CELL(0.438 ns) = 3.619 ns; Loc. = LCCOMB_X33_Y3_N12; Fanout = 3; COMB Node = 'WideNor0~11'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "2.620 ns" { K WideNor0~11 } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(0.660 ns) 4.715 ns Q\[3\] 3 REG LCFF_X32_Y3_N15 6 " "Info: 3: + IC(0.436 ns) + CELL(0.660 ns) = 4.715 ns; Loc. = LCFF_X32_Y3_N15; Fanout = 6; REG Node = 'Q\[3\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.096 ns" { WideNor0~11 Q[3] } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.097 ns ( 44.48 % ) " "Info: Total cell delay = 2.097 ns ( 44.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.618 ns ( 55.52 % ) " "Info: Total interconnect delay = 2.618 ns ( 55.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "4.715 ns" { K WideNor0~11 Q[3] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "4.715 ns" { K K~combout WideNor0~11 Q[3] } { 0.000ns 0.000ns 2.182ns 0.436ns } { 0.000ns 0.999ns 0.438ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "S3 destination 2.296 ns - Shortest register " "Info: - Shortest clock path from clock \"S3\" to destination register is 2.296 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns S3 1 CLK PIN_AE14 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_AE14; Fanout = 1; CLK Node = 'S3'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { S3 } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.760 ns) + CELL(0.537 ns) 2.296 ns Q\[3\] 2 REG LCFF_X32_Y3_N15 6 " "Info: 2: + IC(0.760 ns) + CELL(0.537 ns) = 2.296 ns; Loc. = LCFF_X32_Y3_N15; Fanout = 6; REG Node = 'Q\[3\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.297 ns" { S3 Q[3] } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 66.90 % ) " "Info: Total cell delay = 1.536 ns ( 66.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.760 ns ( 33.10 % ) " "Info: Total interconnect delay = 0.760 ns ( 33.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "2.296 ns" { S3 Q[3] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "2.296 ns" { S3 S3~combout Q[3] } { 0.000ns 0.000ns 0.760ns } { 0.000ns 0.999ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "4.715 ns" { K WideNor0~11 Q[3] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "4.715 ns" { K K~combout WideNor0~11 Q[3] } { 0.000ns 0.000ns 2.182ns 0.436ns } { 0.000ns 0.999ns 0.438ns 0.660ns } "" } } { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "2.296 ns" { S3 Q[3] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "2.296 ns" { S3 S3~combout Q[3] } { 0.000ns 0.000ns 0.760ns } { 0.000ns 0.999ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "S2 HEX0\[2\] Q\[2\] 8.859 ns register " "Info: tco from clock \"S2\" to destination pin \"HEX0\[2\]\" through register \"Q\[2\]\" is 8.859 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "S2 source 3.713 ns + Longest register " "Info: + Longest clock path from clock \"S2\" to source register is 3.713 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns S2 1 CLK PIN_P25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P25; Fanout = 1; CLK Node = 'S2'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { S2 } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.177 ns) + CELL(0.537 ns) 3.713 ns Q\[2\] 2 REG LCFF_X33_Y3_N17 6 " "Info: 2: + IC(2.177 ns) + CELL(0.537 ns) = 3.713 ns; Loc. = LCFF_X33_Y3_N17; Fanout = 6; REG Node = 'Q\[2\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "2.714 ns" { S2 Q[2] } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 41.37 % ) " "Info: Total cell delay = 1.536 ns ( 41.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.177 ns ( 58.63 % ) " "Info: Total interconnect delay = 2.177 ns ( 58.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "3.713 ns" { S2 Q[2] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "3.713 ns" { S2 S2~combout Q[2] } { 0.000ns 0.000ns 2.177ns } { 0.000ns 0.999ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.896 ns + Longest register pin " "Info: + Longest register to pin delay is 4.896 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q\[2\] 1 REG LCFF_X33_Y3_N17 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y3_N17; Fanout = 6; REG Node = 'Q\[2\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q[2] } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.557 ns) + CELL(0.416 ns) 0.973 ns Decoder0~54 2 COMB LCCOMB_X33_Y3_N18 1 " "Info: 2: + IC(0.557 ns) + CELL(0.416 ns) = 0.973 ns; Loc. = LCCOMB_X33_Y3_N18; Fanout = 1; COMB Node = 'Decoder0~54'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "0.973 ns" { Q[2] Decoder0~54 } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.145 ns) + CELL(2.778 ns) 4.896 ns HEX0\[2\] 3 PIN PIN_AC12 0 " "Info: 3: + IC(1.145 ns) + CELL(2.778 ns) = 4.896 ns; Loc. = PIN_AC12; Fanout = 0; PIN Node = 'HEX0\[2\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "3.923 ns" { Decoder0~54 HEX0[2] } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.194 ns ( 65.24 % ) " "Info: Total cell delay = 3.194 ns ( 65.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.702 ns ( 34.76 % ) " "Info: Total interconnect delay = 1.702 ns ( 34.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "4.896 ns" { Q[2] Decoder0~54 HEX0[2] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "4.896 ns" { Q[2] Decoder0~54 HEX0[2] } { 0.000ns 0.557ns 1.145ns } { 0.000ns 0.416ns 2.778ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "3.713 ns" { S2 Q[2] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "3.713 ns" { S2 S2~combout Q[2] } { 0.000ns 0.000ns 2.177ns } { 0.000ns 0.999ns 0.537ns } "" } } { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "4.896 ns" { Q[2] Decoder0~54 HEX0[2] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "4.896 ns" { Q[2] Decoder0~54 HEX0[2] } { 0.000ns 0.557ns 1.145ns } { 0.000ns 0.416ns 2.778ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}