prev_cmp_qiangdaqi.tan.qmsg

用verilog实现的抢答器程序,在Quartus II上编译通过并成功运行

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "S1 " "Info: Assuming node \"S1\" is an undefined clock" {  } { { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 2 -1 0 } } { "d:/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus/bin/Assignment Editor.qase" 1 { { 0 "S1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "S2 " "Info: Assuming node \"S2\" is an undefined clock" {  } { { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 2 -1 0 } } { "d:/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus/bin/Assignment Editor.qase" 1 { { 0 "S2" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "S3 " "Info: Assuming node \"S3\" is an undefined clock" {  } { { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 2 -1 0 } } { "d:/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus/bin/Assignment Editor.qase" 1 { { 0 "S3" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "S1 register register Q\[1\] Q\[1\] 420.17 MHz Internal " "Info: Clock \"S1\" Internal fmax is restricted to 420.17 MHz between source register \"Q\[1\]\" and destination register \"Q\[1\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.780 ns + Longest register register " "Info: + Longest register to register delay is 1.780 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q\[1\] 1 REG LCFF_X30_Y35_N29 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y35_N29; Fanout = 6; REG Node = 'Q\[1\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q[1] } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.310 ns) + CELL(0.376 ns) 0.686 ns WideNor0~11 2 COMB LCCOMB_X30_Y35_N20 3 " "Info: 2: + IC(0.310 ns) + CELL(0.376 ns) = 0.686 ns; Loc. = LCCOMB_X30_Y35_N20; Fanout = 3; COMB Node = 'WideNor0~11'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "0.686 ns" { Q[1] WideNor0~11 } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.660 ns) 1.780 ns Q\[1\] 3 REG LCFF_X30_Y35_N29 6 " "Info: 3: + IC(0.434 ns) + CELL(0.660 ns) = 1.780 ns; Loc. = LCFF_X30_Y35_N29; Fanout = 6; REG Node = 'Q\[1\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.094 ns" { WideNor0~11 Q[1] } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.036 ns ( 58.20 % ) " "Info: Total cell delay = 1.036 ns ( 58.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.744 ns ( 41.80 % ) " "Info: Total interconnect delay = 0.744 ns ( 41.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.780 ns" { Q[1] WideNor0~11 Q[1] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "1.780 ns" { Q[1] WideNor0~11 Q[1] } { 0.000ns 0.310ns 0.434ns } { 0.000ns 0.376ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "S1 destination 2.135 ns + Shortest register " "Info: + Shortest clock path from clock \"S1\" to destination register is 2.135 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns S1 1 CLK PIN_C13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; CLK Node = 'S1'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { S1 } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.619 ns) + CELL(0.537 ns) 2.135 ns Q\[1\] 2 REG LCFF_X30_Y35_N29 6 " "Info: 2: + IC(0.619 ns) + CELL(0.537 ns) = 2.135 ns; Loc. = LCFF_X30_Y35_N29; Fanout = 6; REG Node = 'Q\[1\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.156 ns" { S1 Q[1] } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 71.01 % ) " "Info: Total cell delay = 1.516 ns ( 71.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.619 ns ( 28.99 % ) " "Info: Total interconnect delay = 0.619 ns ( 28.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "2.135 ns" { S1 Q[1] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "2.135 ns" { S1 S1~combout Q[1] } { 0.000ns 0.000ns 0.619ns } { 0.000ns 0.979ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "S1 source 2.135 ns - Longest register " "Info: - Longest clock path from clock \"S1\" to source register is 2.135 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns S1 1 CLK PIN_C13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; CLK Node = 'S1'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { S1 } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.619 ns) + CELL(0.537 ns) 2.135 ns Q\[1\] 2 REG LCFF_X30_Y35_N29 6 " "Info: 2: + IC(0.619 ns) + CELL(0.537 ns) = 2.135 ns; Loc. = LCFF_X30_Y35_N29; Fanout = 6; REG Node = 'Q\[1\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.156 ns" { S1 Q[1] } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 71.01 % ) " "Info: Total cell delay = 1.516 ns ( 71.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.619 ns ( 28.99 % ) " "Info: Total interconnect delay = 0.619 ns ( 28.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "2.135 ns" { S1 Q[1] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "2.135 ns" { S1 S1~combout Q[1] } { 0.000ns 0.000ns 0.619ns } { 0.000ns 0.979ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "2.135 ns" { S1 Q[1] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "2.135 ns" { S1 S1~combout Q[1] } { 0.000ns 0.000ns 0.619ns } { 0.000ns 0.979ns 0.537ns } "" } } { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "2.135 ns" { S1 Q[1] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "2.135 ns" { S1 S1~combout Q[1] } { 0.000ns 0.000ns 0.619ns } { 0.000ns 0.979ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 10 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 10 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.780 ns" { Q[1] WideNor0~11 Q[1] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "1.780 ns" { Q[1] WideNor0~11 Q[1] } { 0.000ns 0.310ns 0.434ns } { 0.000ns 0.376ns 0.660ns } "" } } { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "2.135 ns" { S1 Q[1] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "2.135 ns" { S1 S1~combout Q[1] } { 0.000ns 0.000ns 0.619ns } { 0.000ns 0.979ns 0.537ns } "" } } { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "2.135 ns" { S1 Q[1] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "2.135 ns" { S1 S1~combout Q[1] } { 0.000ns 0.000ns 0.619ns } { 0.000ns 0.979ns 0.537ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q[1] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "" { Q[1] } {  } {  } "" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 10 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "S2 register register Q\[2\] Q\[2\] 450.05 MHz Internal " "Info: Clock \"S2\" Internal fmax is restricted to 450.05 MHz between source register \"Q\[2\]\" and destination register \"Q\[2\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.222 ns " "Info: fmax restricted to clock pin edge rate 2.222 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.480 ns + Longest register register " "Info: + Longest register to register delay is 1.480 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q\[2\] 1 REG LCFF_X30_Y35_N9 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y35_N9; Fanout = 6; REG Node = 'Q\[2\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q[2] } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.314 ns) + CELL(0.275 ns) 0.589 ns WideNor0~11 2 COMB LCCOMB_X30_Y35_N20 3 " "Info: 2: + IC(0.314 ns) + CELL(0.275 ns) = 0.589 ns; Loc. = LCCOMB_X30_Y35_N20; Fanout = 3; COMB Node = 'WideNor0~11'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "0.589 ns" { Q[2] WideNor0~11 } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.231 ns) + CELL(0.660 ns) 1.480 ns Q\[2\] 3 REG LCFF_X30_Y35_N9 6 " "Info: 3: + IC(0.231 ns) + CELL(0.660 ns) = 1.480 ns; Loc. = LCFF_X30_Y35_N9; Fanout = 6; REG Node = 'Q\[2\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "0.891 ns" { WideNor0~11 Q[2] } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.935 ns ( 63.18 % ) " "Info: Total cell delay = 0.935 ns ( 63.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.545 ns ( 36.82 % ) " "Info: Total interconnect delay = 0.545 ns ( 36.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.480 ns" { Q[2] WideNor0~11 Q[2] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "1.480 ns" { Q[2] WideNor0~11 Q[2] } { 0.000ns 0.314ns 0.231ns } { 0.000ns 0.275ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "S2 destination 2.336 ns + Shortest register " "Info: + Shortest clock path from clock \"S2\" to destination register is 2.336 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns S2 1 CLK PIN_B11 1 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_B11; Fanout = 1; CLK Node = 'S2'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { S2 } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.949 ns) + CELL(0.537 ns) 2.336 ns Q\[2\] 2 REG LCFF_X30_Y35_N9 6 " "Info: 2: + IC(0.949 ns) + CELL(0.537 ns) = 2.336 ns; Loc. = LCFF_X30_Y35_N9; Fanout = 6; REG Node = 'Q\[2\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.486 ns" { S2 Q[2] } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.387 ns ( 59.38 % ) " "Info: Total cell delay = 1.387 ns ( 59.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.949 ns ( 40.63 % ) " "Info: Total interconnect delay = 0.949 ns ( 40.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "2.336 ns" { S2 Q[2] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "2.336 ns" { S2 S2~combout Q[2] } { 0.000ns 0.000ns 0.949ns } { 0.000ns 0.850ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "S2 source 2.336 ns - Longest register " "Info: - Longest clock path from clock \"S2\" to source register is 2.336 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns S2 1 CLK PIN_B11 1 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_B11; Fanout = 1; CLK Node = 'S2'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { S2 } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.949 ns) + CELL(0.537 ns) 2.336 ns Q\[2\] 2 REG LCFF_X30_Y35_N9 6 " "Info: 2: + IC(0.949 ns) + CELL(0.537 ns) = 2.336 ns; Loc. = LCFF_X30_Y35_N9; Fanout = 6; REG Node = 'Q\[2\]'" {  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.486 ns" { S2 Q[2] } "NODE_NAME" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.387 ns ( 59.38 % ) " "Info: Total cell delay = 1.387 ns ( 59.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.949 ns ( 40.63 % ) " "Info: Total interconnect delay = 0.949 ns ( 40.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "2.336 ns" { S2 Q[2] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "2.336 ns" { S2 S2~combout Q[2] } { 0.000ns 0.000ns 0.949ns } { 0.000ns 0.850ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "2.336 ns" { S2 Q[2] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "2.336 ns" { S2 S2~combout Q[2] } { 0.000ns 0.000ns 0.949ns } { 0.000ns 0.850ns 0.537ns } "" } } { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "2.336 ns" { S2 Q[2] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "2.336 ns" { S2 S2~combout Q[2] } { 0.000ns 0.000ns 0.949ns } { 0.000ns 0.850ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "1.480 ns" { Q[2] WideNor0~11 Q[2] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "1.480 ns" { Q[2] WideNor0~11 Q[2] } { 0.000ns 0.314ns 0.231ns } { 0.000ns 0.275ns 0.660ns } "" } } { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "2.336 ns" { S2 Q[2] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "2.336 ns" { S2 S2~combout Q[2] } { 0.000ns 0.000ns 0.949ns } { 0.000ns 0.850ns 0.537ns } "" } } { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "2.336 ns" { S2 Q[2] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "2.336 ns" { S2 S2~combout Q[2] } { 0.000ns 0.000ns 0.949ns } { 0.000ns 0.850ns 0.537ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q[2] } "NODE_NAME" } } { "d:/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/bin/Technology_Viewer.qrui" "" { Q[2] } {  } {  } "" } } { "qiangdaqi.v" "" { Text "E:/zzs2/qiangdaqi.v" 16 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}