qiangdaqi.fit.summary

用verilog实现的抢答器程序,在Quartus II上编译通过并成功运行

Fitter Status : Successful - Sat Oct 20 00:03:33 2007
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : qiangdaqi
Top-level Entity Name : qiangdaqi
Family : Cyclone II
Device : EP2C35F672C6
Timing Models : Final
Total logic elements : 9 / 33,216 ( < 1 % )
    Total combinational functions : 9 / 33,216 ( < 1 % )
    Dedicated logic registers : 3 / 33,216 ( < 1 % )
Total registers : 3
Total pins : 11 / 475 ( 2 % )
Total virtual pins : 0
Total memory bits : 0 / 483,840 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )