qiangdaqi.map.summary

来自「用verilog实现的抢答器程序,在Quartus II上编译通过并成功运行」· SUMMARY 代码 · 共 15 行

Analysis & Synthesis Status : Successful - Sat Oct 20 00:03:18 2007
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : qiangdaqi
Top-level Entity Name : qiangdaqi
Family : Cyclone II
Total logic elements : 6
    Total combinational functions : 6
    Dedicated logic registers : 3
Total registers : 3
Total pins : 11
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0