qiangdaqi.tan.rpt

用verilog实现的抢答器程序,在Quartus II上编译通过并成功运行

; N/A   ; None         ; 8.575 ns   ; Q[1] ; HEX0[2] ; S1         ;
; N/A   ; None         ; 8.366 ns   ; Q[1] ; HEX0[6] ; S1         ;
; N/A   ; None         ; 8.352 ns   ; Q[1] ; HEX0[5] ; S1         ;
; N/A   ; None         ; 7.732 ns   ; Q[3] ; HEX0[0] ; S3         ;
; N/A   ; None         ; 7.731 ns   ; Q[3] ; HEX0[3] ; S3         ;
; N/A   ; None         ; 7.712 ns   ; Q[3] ; HEX0[2] ; S3         ;
; N/A   ; None         ; 7.687 ns   ; Q[3] ; HEX0[4] ; S3         ;
; N/A   ; None         ; 7.464 ns   ; Q[3] ; HEX0[6] ; S3         ;
; N/A   ; None         ; 7.450 ns   ; Q[3] ; HEX0[5] ; S3         ;
+-------+--------------+------------+------+---------+------------+


+------------------------------------------------------------------+
; th                                                               ;
+---------------+-------------+-----------+------+------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To   ; To Clock ;
+---------------+-------------+-----------+------+------+----------+
; N/A           ; None        ; -0.539 ns ; K    ; Q[2] ; S2       ;
; N/A           ; None        ; -0.822 ns ; K    ; Q[1] ; S1       ;
; N/A           ; None        ; -2.153 ns ; K    ; Q[3] ; S3       ;
+---------------+-------------+-----------+------+------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sat Oct 20 00:03:45 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off qiangdaqi -c qiangdaqi --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "S1" is an undefined clock
    Info: Assuming node "S2" is an undefined clock
    Info: Assuming node "S3" is an undefined clock
Info: Clock "S1" Internal fmax is restricted to 420.17 MHz between source register "Q[1]" and destination register "Q[1]"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.585 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y3_N9; Fanout = 6; REG Node = 'Q[1]'
            Info: 2: + IC(0.310 ns) + CELL(0.376 ns) = 0.686 ns; Loc. = LCCOMB_X33_Y3_N12; Fanout = 3; COMB Node = 'WideNor0~11'
            Info: 3: + IC(0.239 ns) + CELL(0.660 ns) = 1.585 ns; Loc. = LCFF_X33_Y3_N9; Fanout = 6; REG Node = 'Q[1]'
            Info: Total cell delay = 1.036 ns ( 65.36 % )
            Info: Total interconnect delay = 0.549 ns ( 34.64 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "S1" to destination register is 3.430 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N26; Fanout = 1; CLK Node = 'S1'
                Info: 2: + IC(1.894 ns) + CELL(0.537 ns) = 3.430 ns; Loc. = LCFF_X33_Y3_N9; Fanout = 6; REG Node = 'Q[1]'
                Info: Total cell delay = 1.536 ns ( 44.78 % )
                Info: Total interconnect delay = 1.894 ns ( 55.22 % )
            Info: - Longest clock path from clock "S1" to source register is 3.430 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N26; Fanout = 1; CLK Node = 'S1'
                Info: 2: + IC(1.894 ns) + CELL(0.537 ns) = 3.430 ns; Loc. = LCFF_X33_Y3_N9; Fanout = 6; REG Node = 'Q[1]'
                Info: Total cell delay = 1.536 ns ( 44.78 % )
                Info: Total interconnect delay = 1.894 ns ( 55.22 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: Clock "S2" Internal fmax is restricted to 420.17 MHz between source register "Q[2]" and destination register "Q[2]"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.489 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y3_N17; Fanout = 6; REG Node = 'Q[2]'
            Info: 2: + IC(0.315 ns) + CELL(0.275 ns) = 0.590 ns; Loc. = LCCOMB_X33_Y3_N12; Fanout = 3; COMB Node = 'WideNor0~11'
            Info: 3: + IC(0.239 ns) + CELL(0.660 ns) = 1.489 ns; Loc. = LCFF_X33_Y3_N17; Fanout = 6; REG Node = 'Q[2]'
            Info: Total cell delay = 0.935 ns ( 62.79 % )
            Info: Total interconnect delay = 0.554 ns ( 37.21 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "S2" to destination register is 3.713 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P25; Fanout = 1; CLK Node = 'S2'
                Info: 2: + IC(2.177 ns) + CELL(0.537 ns) = 3.713 ns; Loc. = LCFF_X33_Y3_N17; Fanout = 6; REG Node = 'Q[2]'
                Info: Total cell delay = 1.536 ns ( 41.37 % )
                Info: Total interconnect delay = 2.177 ns ( 58.63 % )
            Info: - Longest clock path from clock "S2" to source register is 3.713 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P25; Fanout = 1; CLK Node = 'S2'
                Info: 2: + IC(2.177 ns) + CELL(0.537 ns) = 3.713 ns; Loc. = LCFF_X33_Y3_N17; Fanout = 6; REG Node = 'Q[2]'
                Info: Total cell delay = 1.536 ns ( 41.37 % )
                Info: Total interconnect delay = 2.177 ns ( 58.63 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: Clock "S3" Internal fmax is restricted to 420.17 MHz between source register "Q[3]" and destination register "Q[3]"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.742 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y3_N15; Fanout = 6; REG Node = 'Q[3]'
            Info: 2: + IC(0.496 ns) + CELL(0.150 ns) = 0.646 ns; Loc. = LCCOMB_X33_Y3_N12; Fanout = 3; COMB Node = 'WideNor0~11'
            Info: 3: + IC(0.436 ns) + CELL(0.660 ns) = 1.742 ns; Loc. = LCFF_X32_Y3_N15; Fanout = 6; REG Node = 'Q[3]'
            Info: Total cell delay = 0.810 ns ( 46.50 % )
            Info: Total interconnect delay = 0.932 ns ( 53.50 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "S3" to destination register is 2.296 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_AE14; Fanout = 1; CLK Node = 'S3'
                Info: 2: + IC(0.760 ns) + CELL(0.537 ns) = 2.296 ns; Loc. = LCFF_X32_Y3_N15; Fanout = 6; REG Node = 'Q[3]'
                Info: Total cell delay = 1.536 ns ( 66.90 % )
                Info: Total interconnect delay = 0.760 ns ( 33.10 % )
            Info: - Longest clock path from clock "S3" to source register is 2.296 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_AE14; Fanout = 1; CLK Node = 'S3'
                Info: 2: + IC(0.760 ns) + CELL(0.537 ns) = 2.296 ns; Loc. = LCFF_X32_Y3_N15; Fanout = 6; REG Node = 'Q[3]'
                Info: Total cell delay = 1.536 ns ( 66.90 % )
                Info: Total interconnect delay = 0.760 ns ( 33.10 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "Q[3]" (data pin = "K", clock pin = "S3") is 2.383 ns
    Info: + Longest pin to register delay is 4.715 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N25; Fanout = 2; PIN Node = 'K'
        Info: 2: + IC(2.182 ns) + CELL(0.438 ns) = 3.619 ns; Loc. = LCCOMB_X33_Y3_N12; Fanout = 3; COMB Node = 'WideNor0~11'
        Info: 3: + IC(0.436 ns) + CELL(0.660 ns) = 4.715 ns; Loc. = LCFF_X32_Y3_N15; Fanout = 6; REG Node = 'Q[3]'
        Info: Total cell delay = 2.097 ns ( 44.48 % )
        Info: Total interconnect delay = 2.618 ns ( 55.52 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "S3" to destination register is 2.296 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_AE14; Fanout = 1; CLK Node = 'S3'
        Info: 2: + IC(0.760 ns) + CELL(0.537 ns) = 2.296 ns; Loc. = LCFF_X32_Y3_N15; Fanout = 6; REG Node = 'Q[3]'
        Info: Total cell delay = 1.536 ns ( 66.90 % )
        Info: Total interconnect delay = 0.760 ns ( 33.10 % )
Info: tco from clock "S2" to destination pin "HEX0[2]" through register "Q[2]" is 8.859 ns
    Info: + Longest clock path from clock "S2" to source register is 3.713 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P25; Fanout = 1; CLK Node = 'S2'
        Info: 2: + IC(2.177 ns) + CELL(0.537 ns) = 3.713 ns; Loc. = LCFF_X33_Y3_N17; Fanout = 6; REG Node = 'Q[2]'
        Info: Total cell delay = 1.536 ns ( 41.37 % )
        Info: Total interconnect delay = 2.177 ns ( 58.63 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 4.896 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y3_N17; Fanout = 6; REG Node = 'Q[2]'
        Info: 2: + IC(0.557 ns) + CELL(0.416 ns) = 0.973 ns; Loc. = LCCOMB_X33_Y3_N18; Fanout = 1; COMB Node = 'Decoder0~54'
        Info: 3: + IC(1.145 ns) + CELL(2.778 ns) = 4.896 ns; Loc. = PIN_AC12; Fanout = 0; PIN Node = 'HEX0[2]'
        Info: Total cell delay = 3.194 ns ( 65.24 % )
        Info: Total interconnect delay = 1.702 ns ( 34.76 % )
Info: th for register "Q[2]" (data pin = "K", clock pin = "S2") is -0.539 ns
    Info: + Longest clock path from clock "S2" to destination register is 3.713 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P25; Fanout = 1; CLK Node = 'S2'
        Info: 2: + IC(2.177 ns) + CELL(0.537 ns) = 3.713 ns; Loc. = LCFF_X33_Y3_N17; Fanout = 6; REG Node = 'Q[2]'
        Info: Total cell delay = 1.536 ns ( 41.37 % )
        Info: Total interconnect delay = 2.177 ns ( 58.63 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 4.518 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N25; Fanout = 2; PIN Node = 'K'
        Info: 2: + IC(2.182 ns) + CELL(0.438 ns) = 3.619 ns; Loc. = LCCOMB_X33_Y3_N12; Fanout = 3; COMB Node = 'WideNor0~11'
        Info: 3: + IC(0.239 ns) + CELL(0.660 ns) = 4.518 ns; Loc. = LCFF_X33_Y3_N17; Fanout = 6; REG Node = 'Q[2]'
        Info: Total cell delay = 2.097 ns ( 46.41 % )
        Info: Total interconnect delay = 2.421 ns ( 53.59 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 111 megabytes of memory during processing
    Info: Processing ended: Sat Oct 20 00:03:47 2007
    Info: Elapsed time: 00:00:02