qiangdaqi.tan.rpt

用verilog实现的抢答器程序,在Quartus II上编译通过并成功运行

Classic Timing Analyzer report for qiangdaqi
Sat Oct 20 00:03:46 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'S1'
  6. Clock Setup: 'S2'
  7. Clock Setup: 'S3'
  8. tsu
  9. tco
 10. th
 11. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                       ;
+------------------------------+-------+---------------+------------------------------------------------+------+---------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From ; To      ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+------+---------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 2.383 ns                                       ; K    ; Q[3]    ; --         ; S3       ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 8.859 ns                                       ; Q[2] ; HEX0[2] ; S2         ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -0.539 ns                                      ; K    ; Q[2]    ; --         ; S2       ; 0            ;
; Clock Setup: 'S3'            ; N/A   ; None          ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; Q[3] ; Q[3]    ; S3         ; S3       ; 0            ;
; Clock Setup: 'S2'            ; N/A   ; None          ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; Q[2] ; Q[2]    ; S2         ; S2       ; 0            ;
; Clock Setup: 'S1'            ; N/A   ; None          ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; Q[1] ; Q[1]    ; S1         ; S1       ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;      ;         ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+------+---------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; S1              ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; S2              ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; S3              ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'S1'                                                                                                                                                                ;
+-------+------------------------------------------------+------+------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From ; To   ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------+------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; Q[1] ; Q[1] ; S1         ; S1       ; None                        ; None                      ; 1.585 ns                ;
+-------+------------------------------------------------+------+------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'S2'                                                                                                                                                                ;
+-------+------------------------------------------------+------+------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From ; To   ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------+------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; Q[2] ; Q[2] ; S2         ; S2       ; None                        ; None                      ; 1.489 ns                ;
+-------+------------------------------------------------+------+------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'S3'                                                                                                                                                                ;
+-------+------------------------------------------------+------+------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From ; To   ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------+------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; Q[3] ; Q[3] ; S3         ; S3       ; None                        ; None                      ; 1.742 ns                ;
+-------+------------------------------------------------+------+------+------------+----------+-----------------------------+---------------------------+-------------------------+


+------------------------------------------------------------+
; tsu                                                        ;
+-------+--------------+------------+------+------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To   ; To Clock ;
+-------+--------------+------------+------+------+----------+
; N/A   ; None         ; 2.383 ns   ; K    ; Q[3] ; S3       ;
; N/A   ; None         ; 1.052 ns   ; K    ; Q[1] ; S1       ;
; N/A   ; None         ; 0.769 ns   ; K    ; Q[2] ; S2       ;
+-------+--------------+------------+------+------+----------+


+-----------------------------------------------------------------+
; tco                                                             ;
+-------+--------------+------------+------+---------+------------+
; Slack ; Required tco ; Actual tco ; From ; To      ; From Clock ;
+-------+--------------+------------+------+---------+------------+
; N/A   ; None         ; 8.859 ns   ; Q[2] ; HEX0[2] ; S2         ;
; N/A   ; None         ; 8.841 ns   ; Q[2] ; HEX0[0] ; S2         ;
; N/A   ; None         ; 8.840 ns   ; Q[2] ; HEX0[3] ; S2         ;
; N/A   ; None         ; 8.796 ns   ; Q[2] ; HEX0[4] ; S2         ;
; N/A   ; None         ; 8.635 ns   ; Q[1] ; HEX0[0] ; S1         ;
; N/A   ; None         ; 8.634 ns   ; Q[1] ; HEX0[3] ; S1         ;
; N/A   ; None         ; 8.617 ns   ; Q[2] ; HEX0[6] ; S2         ;
; N/A   ; None         ; 8.605 ns   ; Q[2] ; HEX0[5] ; S2         ;
; N/A   ; None         ; 8.589 ns   ; Q[1] ; HEX0[4] ; S1         ;