qiangdaqi.v

来自「用verilog实现的抢答器程序,在Quartus II上编译通过并成功运行」· Verilog 代码 · 共 35 行

module qiangdaqi(K,S1,S2,S3,HEX0);
input  K,S1,S2,S3; 
output reg[6:0] HEX0;
reg [3:1]   Q;
wire   ena;
assign  ena=~|{~K,Q};
always @(negedge S1 or negedge K)
begin 
if (~K) Q[1] =0;
 else if (ena) Q[1] =1;
  else Q[1] =Q[1];
end
always @(negedge S2 or negedge K)
begin 
if (~K) Q[2] =0;
  else  if(ena) Q[2] =1;
  else Q[2] =Q[2];
end
always @(negedge S3 or negedge K)
begin 
if (~K) Q[3] =0;
  else  if(ena) Q[3] =1;
  else Q[3] =Q[3];
end
always @(Q)
begin
case (Q)
   'b000:HEX0='b1000000;
   'b001:HEX0='b1111001;
   'b010:HEX0='b0100100;
   'b100:HEX0='b0110000;
     default :HEX0='b1000000;
endcase
end
endmodule