qiangdaqi.tan.summary

用verilog实现的抢答器程序,在Quartus II上编译通过并成功运行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 2.383 ns
From           : K
To             : Q[3]
From Clock     : --
To Clock       : S3
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.859 ns
From           : Q[2]
To             : HEX0[2]
From Clock     : S2
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.539 ns
From           : K
To             : Q[2]
From Clock     : --
To Clock       : S2
Failed Paths   : 0

Type           : Clock Setup: 'S3'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 420.17 MHz ( period = 2.380 ns )
From           : Q[3]
To             : Q[3]
From Clock     : S3
To Clock       : S3
Failed Paths   : 0

Type           : Clock Setup: 'S2'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 420.17 MHz ( period = 2.380 ns )
From           : Q[2]
To             : Q[2]
From Clock     : S2
To Clock       : S2
Failed Paths   : 0

Type           : Clock Setup: 'S1'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 420.17 MHz ( period = 2.380 ns )
From           : Q[1]
To             : Q[1]
From Clock     : S1
To Clock       : S1
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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