cnt24.tan.rpt

用verilog实现的记时器程序,在Quartus II上编译通过并成功运行

    Info: Assuming node "clk" is an undefined clock
    Info: Assuming node "js" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "always0~0" as buffer
Info: Clock "clk" has Internal fmax of 408.16 MHz between source register "q_temp[0]" and destination register "q_temp[4]" (period= 2.45 ns)
    Info: + Longest register to register delay is 2.236 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X36_Y28_N11; Fanout = 4; REG Node = 'q_temp[0]'
        Info: 2: + IC(0.343 ns) + CELL(0.414 ns) = 0.757 ns; Loc. = LCCOMB_X36_Y28_N10; Fanout = 2; COMB Node = 'Add0~97'
        Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.828 ns; Loc. = LCCOMB_X36_Y28_N12; Fanout = 2; COMB Node = 'Add0~99'
        Info: 4: + IC(0.000 ns) + CELL(0.159 ns) = 0.987 ns; Loc. = LCCOMB_X36_Y28_N14; Fanout = 2; COMB Node = 'Add0~101'
        Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.058 ns; Loc. = LCCOMB_X36_Y28_N16; Fanout = 2; COMB Node = 'Add0~103'
        Info: 6: + IC(0.000 ns) + CELL(0.410 ns) = 1.468 ns; Loc. = LCCOMB_X36_Y28_N18; Fanout = 1; COMB Node = 'Add0~104'
        Info: 7: + IC(0.264 ns) + CELL(0.420 ns) = 2.152 ns; Loc. = LCCOMB_X36_Y28_N4; Fanout = 1; COMB Node = 'q_temp~110'
        Info: 8: + IC(0.000 ns) + CELL(0.084 ns) = 2.236 ns; Loc. = LCFF_X36_Y28_N5; Fanout = 11; REG Node = 'q_temp[4]'
        Info: Total cell delay = 1.629 ns ( 72.85 % )
        Info: Total interconnect delay = 0.607 ns ( 27.15 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.952 ns
            Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.630 ns) + CELL(0.150 ns) = 1.759 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 1; COMB Node = 'always0~0'
            Info: 3: + IC(0.677 ns) + CELL(0.000 ns) = 2.436 ns; Loc. = CLKCTRL_G9; Fanout = 8; COMB Node = 'always0~0clkctrl'
            Info: 4: + IC(0.979 ns) + CELL(0.537 ns) = 3.952 ns; Loc. = LCFF_X36_Y28_N5; Fanout = 11; REG Node = 'q_temp[4]'
            Info: Total cell delay = 1.666 ns ( 42.16 % )
            Info: Total interconnect delay = 2.286 ns ( 57.84 % )
        Info: - Longest clock path from clock "clk" to source register is 3.952 ns
            Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.630 ns) + CELL(0.150 ns) = 1.759 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 1; COMB Node = 'always0~0'
            Info: 3: + IC(0.677 ns) + CELL(0.000 ns) = 2.436 ns; Loc. = CLKCTRL_G9; Fanout = 8; COMB Node = 'always0~0clkctrl'
            Info: 4: + IC(0.979 ns) + CELL(0.537 ns) = 3.952 ns; Loc. = LCFF_X36_Y28_N11; Fanout = 4; REG Node = 'q_temp[0]'
            Info: Total cell delay = 1.666 ns ( 42.16 % )
            Info: Total interconnect delay = 2.286 ns ( 57.84 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: Clock "js" has Internal fmax of 408.16 MHz between source register "q_temp[0]" and destination register "q_temp[4]" (period= 2.45 ns)
    Info: + Longest register to register delay is 2.236 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X36_Y28_N11; Fanout = 4; REG Node = 'q_temp[0]'
        Info: 2: + IC(0.343 ns) + CELL(0.414 ns) = 0.757 ns; Loc. = LCCOMB_X36_Y28_N10; Fanout = 2; COMB Node = 'Add0~97'
        Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.828 ns; Loc. = LCCOMB_X36_Y28_N12; Fanout = 2; COMB Node = 'Add0~99'
        Info: 4: + IC(0.000 ns) + CELL(0.159 ns) = 0.987 ns; Loc. = LCCOMB_X36_Y28_N14; Fanout = 2; COMB Node = 'Add0~101'
        Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.058 ns; Loc. = LCCOMB_X36_Y28_N16; Fanout = 2; COMB Node = 'Add0~103'
        Info: 6: + IC(0.000 ns) + CELL(0.410 ns) = 1.468 ns; Loc. = LCCOMB_X36_Y28_N18; Fanout = 1; COMB Node = 'Add0~104'
        Info: 7: + IC(0.264 ns) + CELL(0.420 ns) = 2.152 ns; Loc. = LCCOMB_X36_Y28_N4; Fanout = 1; COMB Node = 'q_temp~110'
        Info: 8: + IC(0.000 ns) + CELL(0.084 ns) = 2.236 ns; Loc. = LCFF_X36_Y28_N5; Fanout = 11; REG Node = 'q_temp[4]'
        Info: Total cell delay = 1.629 ns ( 72.85 % )
        Info: Total interconnect delay = 0.607 ns ( 27.15 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "js" to destination register is 4.056 ns
            Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 1; CLK Node = 'js'
            Info: 2: + IC(0.609 ns) + CELL(0.275 ns) = 1.863 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 1; COMB Node = 'always0~0'
            Info: 3: + IC(0.677 ns) + CELL(0.000 ns) = 2.540 ns; Loc. = CLKCTRL_G9; Fanout = 8; COMB Node = 'always0~0clkctrl'
            Info: 4: + IC(0.979 ns) + CELL(0.537 ns) = 4.056 ns; Loc. = LCFF_X36_Y28_N5; Fanout = 11; REG Node = 'q_temp[4]'
            Info: Total cell delay = 1.791 ns ( 44.16 % )
            Info: Total interconnect delay = 2.265 ns ( 55.84 % )
        Info: - Longest clock path from clock "js" to source register is 4.056 ns
            Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 1; CLK Node = 'js'
            Info: 2: + IC(0.609 ns) + CELL(0.275 ns) = 1.863 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 1; COMB Node = 'always0~0'
            Info: 3: + IC(0.677 ns) + CELL(0.000 ns) = 2.540 ns; Loc. = CLKCTRL_G9; Fanout = 8; COMB Node = 'always0~0clkctrl'
            Info: 4: + IC(0.979 ns) + CELL(0.537 ns) = 4.056 ns; Loc. = LCFF_X36_Y28_N11; Fanout = 4; REG Node = 'q_temp[0]'
            Info: Total cell delay = 1.791 ns ( 44.16 % )
            Info: Total interconnect delay = 2.265 ns ( 55.84 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "js" to destination pin "Q[1]" through register "q_temp[5]" is 20.863 ns
    Info: + Longest clock path from clock "js" to source register is 4.056 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 1; CLK Node = 'js'
        Info: 2: + IC(0.609 ns) + CELL(0.275 ns) = 1.863 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 1; COMB Node = 'always0~0'
        Info: 3: + IC(0.677 ns) + CELL(0.000 ns) = 2.540 ns; Loc. = CLKCTRL_G9; Fanout = 8; COMB Node = 'always0~0clkctrl'
        Info: 4: + IC(0.979 ns) + CELL(0.537 ns) = 4.056 ns; Loc. = LCFF_X36_Y28_N21; Fanout = 11; REG Node = 'q_temp[5]'
        Info: Total cell delay = 1.791 ns ( 44.16 % )
        Info: Total interconnect delay = 2.265 ns ( 55.84 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 16.557 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X36_Y28_N21; Fanout = 11; REG Node = 'q_temp[5]'
        Info: 2: + IC(0.817 ns) + CELL(0.393 ns) = 1.210 ns; Loc. = LCCOMB_X36_Y27_N20; Fanout = 2; COMB Node = 'lpm_divide:Mod0|lpm_divide_45m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_3_result_int[1]~11'
        Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 1.281 ns; Loc. = LCCOMB_X36_Y27_N22; Fanout = 2; COMB Node = 'lpm_divide:Mod0|lpm_divide_45m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_3_result_int[2]~13'
        Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.352 ns; Loc. = LCCOMB_X36_Y27_N24; Fanout = 1; COMB Node = 'lpm_divide:Mod0|lpm_divide_45m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_3_result_int[3]~15'
        Info: 5: + IC(0.000 ns) + CELL(0.410 ns) = 1.762 ns; Loc. = LCCOMB_X36_Y27_N26; Fanout = 10; COMB Node = 'lpm_divide:Mod0|lpm_divide_45m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_3_result_int[4]~16'
        Info: 6: + IC(1.252 ns) + CELL(0.150 ns) = 3.164 ns; Loc. = LCCOMB_X36_Y28_N0; Fanout = 1; COMB Node = 'lpm_divide:Mod0|lpm_divide_45m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|StageOut[18]~41'
        Info: 7: + IC(0.956 ns) + CELL(0.393 ns) = 4.513 ns; Loc. = LCCOMB_X36_Y26_N26; Fanout = 1; COMB Node = 'lpm_divide:Mod0|lpm_divide_45m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_4_result_int[4]~19'
        Info: 8: + IC(0.000 ns) + CELL(0.410 ns) = 4.923 ns; Loc. = LCCOMB_X36_Y26_N28; Fanout = 10; COMB Node = 'lpm_divide:Mod0|lpm_divide_45m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_4_result_int[5]~20'
        Info: 9: + IC(0.476 ns) + CELL(0.419 ns) = 5.818 ns; Loc. = LCCOMB_X35_Y26_N10; Fanout = 3; COMB Node = 'lpm_divide:Mod0|lpm_divide_45m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|StageOut[22]~782'
        Info: 10: + IC(0.449 ns) + CELL(0.414 ns) = 6.681 ns; Loc. = LCCOMB_X36_Y26_N4; Fanout = 1; COMB Node = 'lpm_divide:Mod0|lpm_divide_45m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_5_result_int[3]~17'
        Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 6.752 ns; Loc. = LCCOMB_X36_Y26_N6; Fanout = 1; COMB Node = 'lpm_divide:Mod0|lpm_divide_45m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_5_result_int[4]~19'
        Info: 12: + IC(0.000 ns) + CELL(0.410 ns) = 7.162 ns; Loc. = LCCOMB_X36_Y26_N8; Fanout = 10; COMB Node = 'lpm_divide:Mod0|lpm_divide_45m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_5_result_int[5]~20'
        Info: 13: + IC(0.519 ns) + CELL(0.275 ns) = 7.956 ns; Loc. = LCCOMB_X35_Y26_N2; Fanout = 2; COMB Node = 'lpm_divide:Mod0|lpm_divide_45m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|StageOut[27]~27'
        Info: 14: + IC(0.447 ns) + CELL(0.414 ns) = 8.817 ns; Loc. = LCCOMB_X35_Y26_N22; Fanout = 1; COMB Node = 'lpm_divide:Mod0|lpm_divide_45m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_6_result_int[3]~17'
        Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 8.888 ns; Loc. = LCCOMB_X35_Y26_N24; Fanout = 1; COMB Node = 'lpm_divide:Mod0|lpm_divide_45m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_6_result_int[4]~19'
        Info: 16: + IC(0.000 ns) + CELL(0.410 ns) = 9.298 ns; Loc. = LCCOMB_X35_Y26_N26; Fanout = 8; COMB Node = 'lpm_divide:Mod0|lpm_divide_45m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_6_result_int[5]~20'
        Info: 17: + IC(0.519 ns) + CELL(0.437 ns) = 10.254 ns; Loc. = LCCOMB_X34_Y26_N22; Fanout = 3; COMB Node = 'lpm_divide:Mod0|lpm_divide_45m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|StageOut[32]~786'
        Info: 18: + IC(0.449 ns) + CELL(0.414 ns) = 11.117 ns; Loc. = LCCOMB_X34_Y26_N6; Fanout = 1; COMB Node = 'lpm_divide:Mod0|lpm_divide_45m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_7_result_int[3]~17'
        Info: 19: + IC(0.000 ns) + CELL(0.071 ns) = 11.188 ns; Loc. = LCCOMB_X34_Y26_N8; Fanout = 1; COMB Node = 'lpm_divide:Mod0|lpm_divide_45m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_7_result_int[4]~19'
        Info: 20: + IC(0.000 ns) + CELL(0.410 ns) = 11.598 ns; Loc. = LCCOMB_X34_Y26_N10; Fanout = 3; COMB Node = 'lpm_divide:Mod0|lpm_divide_45m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_7_result_int[5]~20'
        Info: 21: + IC(0.283 ns) + CELL(0.437 ns) = 12.318 ns; Loc. = LCCOMB_X34_Y26_N28; Fanout = 1; COMB Node = 'lpm_divide:Mod0|lpm_divide_45m:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|StageOut[36]~787'
        Info: 22: + IC(1.451 ns) + CELL(2.788 ns) = 16.557 ns; Loc. = PIN_C12; Fanout = 0; PIN Node = 'Q[1]'
        Info: Total cell delay = 8.939 ns ( 53.99 % )
        Info: Total interconnect delay = 7.618 ns ( 46.01 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Tue Oct 16 17:00:42 2007
    Info: Elapsed time: 00:00:01