clk_1hz.tan.qmsg

用verilog实现的记时器程序,在Quartus II上编译通过并成功运行

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register q_temp\[18\] register cout~reg0 160.15 MHz 6.244 ns Internal " "Info: Clock \"clk\" has Internal fmax of 160.15 MHz between source register \"q_temp\[18\]\" and destination register \"cout~reg0\" (period= 6.244 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.030 ns + Longest register register " "Info: + Longest register to register delay is 6.030 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q_temp\[18\] 1 REG LCFF_X56_Y13_N13 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X56_Y13_N13; Fanout = 4; REG Node = 'q_temp\[18\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { q_temp[18] } "NODE_NAME" } } { "CLK_1HZ.v" "" { Text "E:/liao/CLK_1HZ.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.813 ns) + CELL(0.438 ns) 1.251 ns LessThan0~402 2 COMB LCCOMB_X55_Y13_N14 1 " "Info: 2: + IC(0.813 ns) + CELL(0.438 ns) = 1.251 ns; Loc. = LCCOMB_X55_Y13_N14; Fanout = 1; COMB Node = 'LessThan0~402'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.251 ns" { q_temp[18] LessThan0~402 } "NODE_NAME" } } { "CLK_1HZ.v" "" { Text "E:/liao/CLK_1HZ.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.448 ns) + CELL(0.149 ns) 1.848 ns LessThan0~403 3 COMB LCCOMB_X56_Y13_N18 1 " "Info: 3: + IC(0.448 ns) + CELL(0.149 ns) = 1.848 ns; Loc. = LCCOMB_X56_Y13_N18; Fanout = 1; COMB Node = 'LessThan0~403'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.597 ns" { LessThan0~402 LessThan0~403 } "NODE_NAME" } } { "CLK_1HZ.v" "" { Text "E:/liao/CLK_1HZ.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.255 ns) + CELL(0.420 ns) 2.523 ns LessThan0~404 4 COMB LCCOMB_X56_Y13_N0 27 " "Info: 4: + IC(0.255 ns) + CELL(0.420 ns) = 2.523 ns; Loc. = LCCOMB_X56_Y13_N0; Fanout = 27; COMB Node = 'LessThan0~404'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.675 ns" { LessThan0~403 LessThan0~404 } "NODE_NAME" } } { "CLK_1HZ.v" "" { Text "E:/liao/CLK_1HZ.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.744 ns) + CELL(0.150 ns) 3.417 ns Add0~2370 5 COMB LCCOMB_X57_Y12_N26 2 " "Info: 5: + IC(0.744 ns) + CELL(0.150 ns) = 3.417 ns; Loc. = LCCOMB_X57_Y12_N26; Fanout = 2; COMB Node = 'Add0~2370'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.894 ns" { LessThan0~404 Add0~2370 } "NODE_NAME" } } { "CLK_1HZ.v" "" { Text "E:/liao/CLK_1HZ.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.171 ns) + CELL(0.150 ns) 4.738 ns Equal0~338 6 COMB LCCOMB_X56_Y13_N20 1 " "Info: 6: + IC(1.171 ns) + CELL(0.150 ns) = 4.738 ns; Loc. = LCCOMB_X56_Y13_N20; Fanout = 1; COMB Node = 'Equal0~338'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.321 ns" { Add0~2370 Equal0~338 } "NODE_NAME" } } { "CLK_1HZ.v" "" { Text "E:/liao/CLK_1HZ.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.254 ns) + CELL(0.275 ns) 5.267 ns Equal0~339 7 COMB LCCOMB_X56_Y13_N24 1 " "Info: 7: + IC(0.254 ns) + CELL(0.275 ns) = 5.267 ns; Loc. = LCCOMB_X56_Y13_N24; Fanout = 1; COMB Node = 'Equal0~339'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.529 ns" { Equal0~338 Equal0~339 } "NODE_NAME" } } { "CLK_1HZ.v" "" { Text "E:/liao/CLK_1HZ.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.269 ns) + CELL(0.410 ns) 5.946 ns Equal0~345 8 COMB LCCOMB_X56_Y13_N4 1 " "Info: 8: + IC(0.269 ns) + CELL(0.410 ns) = 5.946 ns; Loc. = LCCOMB_X56_Y13_N4; Fanout = 1; COMB Node = 'Equal0~345'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.679 ns" { Equal0~339 Equal0~345 } "NODE_NAME" } } { "CLK_1HZ.v" "" { Text "E:/liao/CLK_1HZ.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.030 ns cout~reg0 9 REG LCFF_X56_Y13_N5 1 " "Info: 9: + IC(0.000 ns) + CELL(0.084 ns) = 6.030 ns; Loc. = LCFF_X56_Y13_N5; Fanout = 1; REG Node = 'cout~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { Equal0~345 cout~reg0 } "NODE_NAME" } } { "CLK_1HZ.v" "" { Text "E:/liao/CLK_1HZ.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.076 ns ( 34.43 % ) " "Info: Total cell delay = 2.076 ns ( 34.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.954 ns ( 65.57 % ) " "Info: Total interconnect delay = 3.954 ns ( 65.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.030 ns" { q_temp[18] LessThan0~402 LessThan0~403 LessThan0~404 Add0~2370 Equal0~338 Equal0~339 Equal0~345 cout~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.030 ns" { q_temp[18] LessThan0~402 LessThan0~403 LessThan0~404 Add0~2370 Equal0~338 Equal0~339 Equal0~345 cout~reg0 } { 0.000ns 0.813ns 0.448ns 0.255ns 0.744ns 1.171ns 0.254ns 0.269ns 0.000ns } { 0.000ns 0.438ns 0.149ns 0.420ns 0.150ns 0.150ns 0.275ns 0.410ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.671 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.671 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CLK_1HZ.v" "" { Text "E:/liao/CLK_1HZ.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 27 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 27; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "CLK_1HZ.v" "" { Text "E:/liao/CLK_1HZ.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.017 ns) + CELL(0.537 ns) 2.671 ns cout~reg0 3 REG LCFF_X56_Y13_N5 1 " "Info: 3: + IC(1.017 ns) + CELL(0.537 ns) = 2.671 ns; Loc. = LCFF_X56_Y13_N5; Fanout = 1; REG Node = 'cout~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.554 ns" { clk~clkctrl cout~reg0 } "NODE_NAME" } } { "CLK_1HZ.v" "" { Text "E:/liao/CLK_1HZ.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.51 % ) " "Info: Total cell delay = 1.536 ns ( 57.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.135 ns ( 42.49 % ) " "Info: Total interconnect delay = 1.135 ns ( 42.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.671 ns" { clk clk~clkctrl cout~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.671 ns" { clk clk~combout clk~clkctrl cout~reg0 } { 0.000ns 0.000ns 0.118ns 1.017ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.671 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.671 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CLK_1HZ.v" "" { Text "E:/liao/CLK_1HZ.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 27 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 27; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "CLK_1HZ.v" "" { Text "E:/liao/CLK_1HZ.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.017 ns) + CELL(0.537 ns) 2.671 ns q_temp\[18\] 3 REG LCFF_X56_Y13_N13 4 " "Info: 3: + IC(1.017 ns) + CELL(0.537 ns) = 2.671 ns; Loc. = LCFF_X56_Y13_N13; Fanout = 4; REG Node = 'q_temp\[18\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.554 ns" { clk~clkctrl q_temp[18] } "NODE_NAME" } } { "CLK_1HZ.v" "" { Text "E:/liao/CLK_1HZ.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.51 % ) " "Info: Total cell delay = 1.536 ns ( 57.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.135 ns ( 42.49 % ) " "Info: Total interconnect delay = 1.135 ns ( 42.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.671 ns" { clk clk~clkctrl q_temp[18] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.671 ns" { clk clk~combout clk~clkctrl q_temp[18] } { 0.000ns 0.000ns 0.118ns 1.017ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.671 ns" { clk clk~clkctrl cout~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.671 ns" { clk clk~combout clk~clkctrl cout~reg0 } { 0.000ns 0.000ns 0.118ns 1.017ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.671 ns" { clk clk~clkctrl q_temp[18] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.671 ns" { clk clk~combout clk~clkctrl q_temp[18] } { 0.000ns 0.000ns 0.118ns 1.017ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "CLK_1HZ.v" "" { Text "E:/liao/CLK_1HZ.v" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "CLK_1HZ.v" "" { Text "E:/liao/CLK_1HZ.v" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.030 ns" { q_temp[18] LessThan0~402 LessThan0~403 LessThan0~404 Add0~2370 Equal0~338 Equal0~339 Equal0~345 cout~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.030 ns" { q_temp[18] LessThan0~402 LessThan0~403 LessThan0~404 Add0~2370 Equal0~338 Equal0~339 Equal0~345 cout~reg0 } { 0.000ns 0.813ns 0.448ns 0.255ns 0.744ns 1.171ns 0.254ns 0.269ns 0.000ns } { 0.000ns 0.438ns 0.149ns 0.420ns 0.150ns 0.150ns 0.275ns 0.410ns 0.084ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.671 ns" { clk clk~clkctrl cout~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.671 ns" { clk clk~combout clk~clkctrl cout~reg0 } { 0.000ns 0.000ns 0.118ns 1.017ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.671 ns" { clk clk~clkctrl q_temp[18] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.671 ns" { clk clk~combout clk~clkctrl q_temp[18] } { 0.000ns 0.000ns 0.118ns 1.017ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk cout cout~reg0 6.709 ns register " "Info: tco from clock \"clk\" to destination pin \"cout\" through register \"cout~reg0\" is 6.709 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.671 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.671 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CLK_1HZ.v" "" { Text "E:/liao/CLK_1HZ.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 27 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 27; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "CLK_1HZ.v" "" { Text "E:/liao/CLK_1HZ.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.017 ns) + CELL(0.537 ns) 2.671 ns cout~reg0 3 REG LCFF_X56_Y13_N5 1 " "Info: 3: + IC(1.017 ns) + CELL(0.537 ns) = 2.671 ns; Loc. = LCFF_X56_Y13_N5; Fanout = 1; REG Node = 'cout~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.554 ns" { clk~clkctrl cout~reg0 } "NODE_NAME" } } { "CLK_1HZ.v" "" { Text "E:/liao/CLK_1HZ.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.51 % ) " "Info: Total cell delay = 1.536 ns ( 57.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.135 ns ( 42.49 % ) " "Info: Total interconnect delay = 1.135 ns ( 42.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.671 ns" { clk clk~clkctrl cout~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.671 ns" { clk clk~combout clk~clkctrl cout~reg0 } { 0.000ns 0.000ns 0.118ns 1.017ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "CLK_1HZ.v" "" { Text "E:/liao/CLK_1HZ.v" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.788 ns + Longest register pin " "Info: + Longest register to pin delay is 3.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cout~reg0 1 REG LCFF_X56_Y13_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X56_Y13_N5; Fanout = 1; REG Node = 'cout~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cout~reg0 } "NODE_NAME" } } { "CLK_1HZ.v" "" { Text "E:/liao/CLK_1HZ.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.146 ns) + CELL(2.642 ns) 3.788 ns cout 2 PIN PIN_U25 0 " "Info: 2: + IC(1.146 ns) + CELL(2.642 ns) = 3.788 ns; Loc. = PIN_U25; Fanout = 0; PIN Node = 'cout'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.788 ns" { cout~reg0 cout } "NODE_NAME" } } { "CLK_1HZ.v" "" { Text "E:/liao/CLK_1HZ.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.642 ns ( 69.75 % ) " "Info: Total cell delay = 2.642 ns ( 69.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.146 ns ( 30.25 % ) " "Info: Total interconnect delay = 1.146 ns ( 30.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.788 ns" { cout~reg0 cout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.788 ns" { cout~reg0 cout } { 0.000ns 1.146ns } { 0.000ns 2.642ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.671 ns" { clk clk~clkctrl cout~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.671 ns" { clk clk~combout clk~clkctrl cout~reg0 } { 0.000ns 0.000ns 0.118ns 1.017ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.788 ns" { cout~reg0 cout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.788 ns" { cout~reg0 cout } { 0.000ns 1.146ns } { 0.000ns 2.642ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 16 17:09:16 2007 " "Info: Processing ended: Tue Oct 16 17:09:16 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}