cnt60.tan.qmsg

用verilog实现的记时器程序,在Quartus II上编译通过并成功运行

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "always0~0 " "Info: Detected gated clock \"always0~0\" as buffer" {  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "always0~0" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register q_temp\[0\] register q_temp\[4\] 407.5 MHz 2.454 ns Internal " "Info: Clock \"clk\" has Internal fmax of 407.5 MHz between source register \"q_temp\[0\]\" and destination register \"q_temp\[4\]\" (period= 2.454 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.240 ns + Longest register register " "Info: + Longest register to register delay is 2.240 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q_temp\[0\] 1 REG LCFF_X51_Y28_N11 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X51_Y28_N11; Fanout = 4; REG Node = 'q_temp\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { q_temp[0] } "NODE_NAME" } } { "CNT60.v" "" { Text "E:/liao/CNT60.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.414 ns) 0.757 ns Add0~97 2 COMB LCCOMB_X51_Y28_N10 2 " "Info: 2: + IC(0.343 ns) + CELL(0.414 ns) = 0.757 ns; Loc. = LCCOMB_X51_Y28_N10; Fanout = 2; COMB Node = 'Add0~97'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.757 ns" { q_temp[0] Add0~97 } "NODE_NAME" } } { "CNT60.v" "" { Text "E:/liao/CNT60.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.828 ns Add0~99 3 COMB LCCOMB_X51_Y28_N12 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.828 ns; Loc. = LCCOMB_X51_Y28_N12; Fanout = 2; COMB Node = 'Add0~99'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~97 Add0~99 } "NODE_NAME" } } { "CNT60.v" "" { Text "E:/liao/CNT60.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 0.987 ns Add0~101 4 COMB LCCOMB_X51_Y28_N14 2 " "Info: 4: + IC(0.000 ns) + CELL(0.159 ns) = 0.987 ns; Loc. = LCCOMB_X51_Y28_N14; Fanout = 2; COMB Node = 'Add0~101'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.159 ns" { Add0~99 Add0~101 } "NODE_NAME" } } { "CNT60.v" "" { Text "E:/liao/CNT60.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.058 ns Add0~103 5 COMB LCCOMB_X51_Y28_N16 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.058 ns; Loc. = LCCOMB_X51_Y28_N16; Fanout = 2; COMB Node = 'Add0~103'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~101 Add0~103 } "NODE_NAME" } } { "CNT60.v" "" { Text "E:/liao/CNT60.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 1.468 ns Add0~104 6 COMB LCCOMB_X51_Y28_N18 1 " "Info: 6: + IC(0.000 ns) + CELL(0.410 ns) = 1.468 ns; Loc. = LCCOMB_X51_Y28_N18; Fanout = 1; COMB Node = 'Add0~104'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { Add0~103 Add0~104 } "NODE_NAME" } } { "CNT60.v" "" { Text "E:/liao/CNT60.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.268 ns) + CELL(0.420 ns) 2.156 ns q_temp~179 7 COMB LCCOMB_X51_Y28_N0 1 " "Info: 7: + IC(0.268 ns) + CELL(0.420 ns) = 2.156 ns; Loc. = LCCOMB_X51_Y28_N0; Fanout = 1; COMB Node = 'q_temp~179'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.688 ns" { Add0~104 q_temp~179 } "NODE_NAME" } } { "CNT60.v" "" { Text "E:/liao/CNT60.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.240 ns q_temp\[4\] 8 REG LCFF_X51_Y28_N1 11 " "Info: 8: + IC(0.000 ns) + CELL(0.084 ns) = 2.240 ns; Loc. = LCFF_X51_Y28_N1; Fanout = 11; REG Node = 'q_temp\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { q_temp~179 q_temp[4] } "NODE_NAME" } } { "CNT60.v" "" { Text "E:/liao/CNT60.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.629 ns ( 72.72 % ) " "Info: Total cell delay = 1.629 ns ( 72.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.611 ns ( 27.28 % ) " "Info: Total interconnect delay = 0.611 ns ( 27.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.240 ns" { q_temp[0] Add0~97 Add0~99 Add0~101 Add0~103 Add0~104 q_temp~179 q_temp[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.240 ns" { q_temp[0] Add0~97 Add0~99 Add0~101 Add0~103 Add0~104 q_temp~179 q_temp[4] } { 0.000ns 0.343ns 0.000ns 0.000ns 0.000ns 0.000ns 0.268ns 0.000ns } { 0.000ns 0.414ns 0.071ns 0.159ns 0.071ns 0.410ns 0.420ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.955 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.955 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_C13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CNT60.v" "" { Text "E:/liao/CNT60.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.630 ns) + CELL(0.150 ns) 1.759 ns always0~0 2 COMB LCCOMB_X31_Y35_N0 1 " "Info: 2: + IC(0.630 ns) + CELL(0.150 ns) = 1.759 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 1; COMB Node = 'always0~0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.780 ns" { clk always0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.677 ns) + CELL(0.000 ns) 2.436 ns always0~0clkctrl 3 COMB CLKCTRL_G9 8 " "Info: 3: + IC(0.677 ns) + CELL(0.000 ns) = 2.436 ns; Loc. = CLKCTRL_G9; Fanout = 8; COMB Node = 'always0~0clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.677 ns" { always0~0 always0~0clkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.982 ns) + CELL(0.537 ns) 3.955 ns q_temp\[4\] 4 REG LCFF_X51_Y28_N1 11 " "Info: 4: + IC(0.982 ns) + CELL(0.537 ns) = 3.955 ns; Loc. = LCFF_X51_Y28_N1; Fanout = 11; REG Node = 'q_temp\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.519 ns" { always0~0clkctrl q_temp[4] } "NODE_NAME" } } { "CNT60.v" "" { Text "E:/liao/CNT60.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.666 ns ( 42.12 % ) " "Info: Total cell delay = 1.666 ns ( 42.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.289 ns ( 57.88 % ) " "Info: Total interconnect delay = 2.289 ns ( 57.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.955 ns" { clk always0~0 always0~0clkctrl q_temp[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.955 ns" { clk clk~combout always0~0 always0~0clkctrl q_temp[4] } { 0.000ns 0.000ns 0.630ns 0.677ns 0.982ns } { 0.000ns 0.979ns 0.150ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.955 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.955 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_C13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CNT60.v" "" { Text "E:/liao/CNT60.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.630 ns) + CELL(0.150 ns) 1.759 ns always0~0 2 COMB LCCOMB_X31_Y35_N0 1 " "Info: 2: + IC(0.630 ns) + CELL(0.150 ns) = 1.759 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 1; COMB Node = 'always0~0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.780 ns" { clk always0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.677 ns) + CELL(0.000 ns) 2.436 ns always0~0clkctrl 3 COMB CLKCTRL_G9 8 " "Info: 3: + IC(0.677 ns) + CELL(0.000 ns) = 2.436 ns; Loc. = CLKCTRL_G9; Fanout = 8; COMB Node = 'always0~0clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.677 ns" { always0~0 always0~0clkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.982 ns) + CELL(0.537 ns) 3.955 ns q_temp\[0\] 4 REG LCFF_X51_Y28_N11 4 " "Info: 4: + IC(0.982 ns) + CELL(0.537 ns) = 3.955 ns; Loc. = LCFF_X51_Y28_N11; Fanout = 4; REG Node = 'q_temp\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.519 ns" { always0~0clkctrl q_temp[0] } "NODE_NAME" } } { "CNT60.v" "" { Text "E:/liao/CNT60.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.666 ns ( 42.12 % ) " "Info: Total cell delay = 1.666 ns ( 42.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.289 ns ( 57.88 % ) " "Info: Total interconnect delay = 2.289 ns ( 57.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.955 ns" { clk always0~0 always0~0clkctrl q_temp[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.955 ns" { clk clk~combout always0~0 always0~0clkctrl q_temp[0] } { 0.000ns 0.000ns 0.630ns 0.677ns 0.982ns } { 0.000ns 0.979ns 0.150ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.955 ns" { clk always0~0 always0~0clkctrl q_temp[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.955 ns" { clk clk~combout always0~0 always0~0clkctrl q_temp[4] } { 0.000ns 0.000ns 0.630ns 0.677ns 0.982ns } { 0.000ns 0.979ns 0.150ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.955 ns" { clk always0~0 always0~0clkctrl q_temp[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.955 ns" { clk clk~combout always0~0 always0~0clkctrl q_temp[0] } { 0.000ns 0.000ns 0.630ns 0.677ns 0.982ns } { 0.000ns 0.979ns 0.150ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "CNT60.v" "" { Text "E:/liao/CNT60.v" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "CNT60.v" "" { Text "E:/liao/CNT60.v" 9 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.240 ns" { q_temp[0] Add0~97 Add0~99 Add0~101 Add0~103 Add0~104 q_temp~179 q_temp[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.240 ns" { q_temp[0] Add0~97 Add0~99 Add0~101 Add0~103 Add0~104 q_temp~179 q_temp[4] } { 0.000ns 0.343ns 0.000ns 0.000ns 0.000ns 0.000ns 0.268ns 0.000ns } { 0.000ns 0.414ns 0.071ns 0.159ns 0.071ns 0.410ns 0.420ns 0.084ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.955 ns" { clk always0~0 always0~0clkctrl q_temp[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.955 ns" { clk clk~combout always0~0 always0~0clkctrl q_temp[4] } { 0.000ns 0.000ns 0.630ns 0.677ns 0.982ns } { 0.000ns 0.979ns 0.150ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.955 ns" { clk always0~0 always0~0clkctrl q_temp[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.955 ns" { clk clk~combout always0~0 always0~0clkctrl q_temp[0] } { 0.000ns 0.000ns 0.630ns 0.677ns 0.982ns } { 0.000ns 0.979ns 0.150ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}