📄 dec_8421.tan.rpt
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Timing Analyzer report for dec_8421
Tue Oct 09 20:45:25 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+--------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+--------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 10.023 ns ; a[3] ; hex[3] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+--------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C35F672C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+--------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+--------+
; N/A ; None ; 10.023 ns ; a[3] ; hex[3] ;
; N/A ; None ; 10.013 ns ; a[3] ; hex[2] ;
; N/A ; None ; 9.946 ns ; a[2] ; hex[3] ;
; N/A ; None ; 9.943 ns ; a[2] ; hex[2] ;
; N/A ; None ; 9.796 ns ; a[3] ; hex[1] ;
; N/A ; None ; 9.790 ns ; a[3] ; hex[0] ;
; N/A ; None ; 9.767 ns ; a[3] ; hex[5] ;
; N/A ; None ; 9.722 ns ; a[2] ; hex[1] ;
; N/A ; None ; 9.713 ns ; a[2] ; hex[0] ;
; N/A ; None ; 9.662 ns ; a[2] ; hex[5] ;
; N/A ; None ; 9.581 ns ; a[3] ; hex[6] ;
; N/A ; None ; 9.577 ns ; a[3] ; hex[4] ;
; N/A ; None ; 9.511 ns ; a[2] ; hex[6] ;
; N/A ; None ; 9.501 ns ; a[2] ; hex[4] ;
; N/A ; None ; 6.305 ns ; a[1] ; hex[2] ;
; N/A ; None ; 6.302 ns ; a[1] ; hex[3] ;
; N/A ; None ; 6.074 ns ; a[1] ; hex[1] ;
; N/A ; None ; 6.051 ns ; a[1] ; hex[5] ;
; N/A ; None ; 6.042 ns ; a[1] ; hex[0] ;
; N/A ; None ; 6.010 ns ; a[0] ; hex[3] ;
; N/A ; None ; 6.009 ns ; a[0] ; hex[2] ;
; N/A ; None ; 5.862 ns ; a[1] ; hex[6] ;
; N/A ; None ; 5.835 ns ; a[1] ; hex[4] ;
; N/A ; None ; 5.783 ns ; a[0] ; hex[1] ;
; N/A ; None ; 5.780 ns ; a[0] ; hex[0] ;
; N/A ; None ; 5.757 ns ; a[0] ; hex[5] ;
; N/A ; None ; 5.573 ns ; a[0] ; hex[6] ;
; N/A ; None ; 5.570 ns ; a[0] ; hex[4] ;
+-------+-------------------+-----------------+------+--------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Tue Oct 09 20:45:24 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dec_8421 -c dec_8421 --timing_analysis_only
Info: Longest tpd from source pin "a[3]" to destination pin "hex[3]" is 10.023 ns
Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_D16; Fanout = 7; PIN Node = 'a[3]'
Info: 2: + IC(5.090 ns) + CELL(0.275 ns) = 6.205 ns; Loc. = LCCOMB_X36_Y35_N10; Fanout = 1; COMB Node = 'WideOr3~4'
Info: 3: + IC(1.030 ns) + CELL(2.788 ns) = 10.023 ns; Loc. = PIN_C12; Fanout = 0; PIN Node = 'hex[3]'
Info: Total cell delay = 3.903 ns ( 38.94 % )
Info: Total interconnect delay = 6.120 ns ( 61.06 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Tue Oct 09 20:45:24 2007
Info: Elapsed time: 00:00:00
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