clk_1hz.tan.rpt

用verilog实现的记时器程序,在Quartus II上编译通过并成功运行

; N/A                                     ; 271.52 MHz ( period = 3.683 ns )                    ; q_temp[18] ; q_temp[24] ; clk        ; clk      ; None                        ; None                      ; 3.468 ns                ;
; N/A                                     ; 271.59 MHz ( period = 3.682 ns )                    ; q_temp[6]  ; q_temp[17] ; clk        ; clk      ; None                        ; None                      ; 3.469 ns                ;
; N/A                                     ; 271.67 MHz ( period = 3.681 ns )                    ; q_temp[18] ; q_temp[7]  ; clk        ; clk      ; None                        ; None                      ; 3.466 ns                ;
; N/A                                     ; 271.74 MHz ( period = 3.680 ns )                    ; q_temp[18] ; q_temp[20] ; clk        ; clk      ; None                        ; None                      ; 3.465 ns                ;
; N/A                                     ; 271.74 MHz ( period = 3.680 ns )                    ; q_temp[18] ; q_temp[9]  ; clk        ; clk      ; None                        ; None                      ; 3.465 ns                ;
; N/A                                     ; 271.81 MHz ( period = 3.679 ns )                    ; q_temp[18] ; q_temp[12] ; clk        ; clk      ; None                        ; None                      ; 3.465 ns                ;
; N/A                                     ; 271.81 MHz ( period = 3.679 ns )                    ; q_temp[18] ; q_temp[22] ; clk        ; clk      ; None                        ; None                      ; 3.464 ns                ;
; N/A                                     ; 272.03 MHz ( period = 3.676 ns )                    ; q_temp[0]  ; q_temp[13] ; clk        ; clk      ; None                        ; None                      ; 3.462 ns                ;
; N/A                                     ; 272.41 MHz ( period = 3.671 ns )                    ; q_temp[18] ; q_temp[6]  ; clk        ; clk      ; None                        ; None                      ; 3.456 ns                ;
; N/A                                     ; 272.55 MHz ( period = 3.669 ns )                    ; q_temp[12] ; q_temp[25] ; clk        ; clk      ; None                        ; None                      ; 3.455 ns                ;
; N/A                                     ; 272.55 MHz ( period = 3.669 ns )                    ; q_temp[12] ; q_temp[8]  ; clk        ; clk      ; None                        ; None                      ; 3.455 ns                ;
; N/A                                     ; 272.55 MHz ( period = 3.669 ns )                    ; q_temp[18] ; q_temp[16] ; clk        ; clk      ; None                        ; None                      ; 3.454 ns                ;
; N/A                                     ; 272.70 MHz ( period = 3.667 ns )                    ; q_temp[12] ; q_temp[24] ; clk        ; clk      ; None                        ; None                      ; 3.452 ns                ;
; N/A                                     ; 272.70 MHz ( period = 3.667 ns )                    ; q_temp[18] ; q_temp[23] ; clk        ; clk      ; None                        ; None                      ; 3.452 ns                ;
; N/A                                     ; 272.78 MHz ( period = 3.666 ns )                    ; q_temp[11] ; q_temp[25] ; clk        ; clk      ; None                        ; None                      ; 3.452 ns                ;
; N/A                                     ; 272.85 MHz ( period = 3.665 ns )                    ; q_temp[18] ; q_temp[21] ; clk        ; clk      ; None                        ; None                      ; 3.450 ns                ;
; N/A                                     ; 272.85 MHz ( period = 3.665 ns )                    ; q_temp[12] ; q_temp[7]  ; clk        ; clk      ; None                        ; None                      ; 3.450 ns                ;
; N/A                                     ; 272.93 MHz ( period = 3.664 ns )                    ; q_temp[12] ; q_temp[20] ; clk        ; clk      ; None                        ; None                      ; 3.449 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;            ;            ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+-----------+------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To   ; From Clock ;
+-------+--------------+------------+-----------+------+------------+
; N/A   ; None         ; 6.709 ns   ; cout~reg0 ; cout ; clk        ;
+-------+--------------+------------+-----------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Oct 16 17:09:16 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off CLK_1HZ -c CLK_1HZ --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 160.15 MHz between source register "q_temp[18]" and destination register "cout~reg0" (period= 6.244 ns)
    Info: + Longest register to register delay is 6.030 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X56_Y13_N13; Fanout = 4; REG Node = 'q_temp[18]'
        Info: 2: + IC(0.813 ns) + CELL(0.438 ns) = 1.251 ns; Loc. = LCCOMB_X55_Y13_N14; Fanout = 1; COMB Node = 'LessThan0~402'
        Info: 3: + IC(0.448 ns) + CELL(0.149 ns) = 1.848 ns; Loc. = LCCOMB_X56_Y13_N18; Fanout = 1; COMB Node = 'LessThan0~403'
        Info: 4: + IC(0.255 ns) + CELL(0.420 ns) = 2.523 ns; Loc. = LCCOMB_X56_Y13_N0; Fanout = 27; COMB Node = 'LessThan0~404'
        Info: 5: + IC(0.744 ns) + CELL(0.150 ns) = 3.417 ns; Loc. = LCCOMB_X57_Y12_N26; Fanout = 2; COMB Node = 'Add0~2370'
        Info: 6: + IC(1.171 ns) + CELL(0.150 ns) = 4.738 ns; Loc. = LCCOMB_X56_Y13_N20; Fanout = 1; COMB Node = 'Equal0~338'
        Info: 7: + IC(0.254 ns) + CELL(0.275 ns) = 5.267 ns; Loc. = LCCOMB_X56_Y13_N24; Fanout = 1; COMB Node = 'Equal0~339'
        Info: 8: + IC(0.269 ns) + CELL(0.410 ns) = 5.946 ns; Loc. = LCCOMB_X56_Y13_N4; Fanout = 1; COMB Node = 'Equal0~345'
        Info: 9: + IC(0.000 ns) + CELL(0.084 ns) = 6.030 ns; Loc. = LCFF_X56_Y13_N5; Fanout = 1; REG Node = 'cout~reg0'
        Info: Total cell delay = 2.076 ns ( 34.43 % )
        Info: Total interconnect delay = 3.954 ns ( 65.57 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.671 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 27; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.017 ns) + CELL(0.537 ns) = 2.671 ns; Loc. = LCFF_X56_Y13_N5; Fanout = 1; REG Node = 'cout~reg0'
            Info: Total cell delay = 1.536 ns ( 57.51 % )
            Info: Total interconnect delay = 1.135 ns ( 42.49 % )
        Info: - Longest clock path from clock "clk" to source register is 2.671 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 27; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.017 ns) + CELL(0.537 ns) = 2.671 ns; Loc. = LCFF_X56_Y13_N13; Fanout = 4; REG Node = 'q_temp[18]'
            Info: Total cell delay = 1.536 ns ( 57.51 % )
            Info: Total interconnect delay = 1.135 ns ( 42.49 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "clk" to destination pin "cout" through register "cout~reg0" is 6.709 ns
    Info: + Longest clock path from clock "clk" to source register is 2.671 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 27; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.017 ns) + CELL(0.537 ns) = 2.671 ns; Loc. = LCFF_X56_Y13_N5; Fanout = 1; REG Node = 'cout~reg0'
        Info: Total cell delay = 1.536 ns ( 57.51 % )
        Info: Total interconnect delay = 1.135 ns ( 42.49 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.788 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X56_Y13_N5; Fanout = 1; REG Node = 'cout~reg0'
        Info: 2: + IC(1.146 ns) + CELL(2.642 ns) = 3.788 ns; Loc. = PIN_U25; Fanout = 0; PIN Node = 'cout'
        Info: Total cell delay = 2.642 ns ( 69.75 % )
        Info: Total interconnect delay = 1.146 ns ( 30.25 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Oct 16 17:09:16 2007
    Info: Elapsed time: 00:00:01