qiangdaqi.tan.rpt

用verilog实现的记时器程序,在Quartus II上编译通过并成功运行

; N/A   ; None         ; 9.170 ns   ; Q[2] ; HEX0[2] ; S2         ;
; N/A   ; None         ; 9.147 ns   ; Q[2] ; HEX0[3] ; S2         ;
; N/A   ; None         ; 8.970 ns   ; Q[2] ; HEX0[6] ; S2         ;
; N/A   ; None         ; 8.858 ns   ; Q[3] ; HEX0[0] ; S3         ;
; N/A   ; None         ; 8.688 ns   ; Q[3] ; HEX0[5] ; S3         ;
; N/A   ; None         ; 8.649 ns   ; Q[3] ; HEX0[4] ; S3         ;
; N/A   ; None         ; 8.627 ns   ; Q[3] ; HEX0[2] ; S3         ;
; N/A   ; None         ; 8.604 ns   ; Q[3] ; HEX0[3] ; S3         ;
; N/A   ; None         ; 8.433 ns   ; Q[3] ; HEX0[6] ; S3         ;
+-------+--------------+------------+------+---------+------------+


+------------------------------------------------------------------+
; th                                                               ;
+---------------+-------------+-----------+------+------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To   ; To Clock ;
+---------------+-------------+-----------+------+------+----------+
; N/A           ; None        ; -4.828 ns ; K    ; Q[1] ; S1       ;
; N/A           ; None        ; -5.476 ns ; K    ; Q[3] ; S3       ;
; N/A           ; None        ; -5.981 ns ; K    ; Q[2] ; S2       ;
+---------------+-------------+-----------+------+------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Thu Oct 18 23:14:15 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off qiangdaqi -c qiangdaqi --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "S1" is an undefined clock
    Info: Assuming node "S2" is an undefined clock
    Info: Assuming node "S3" is an undefined clock
Info: Clock "S1" Internal fmax is restricted to 450.05 MHz between source register "Q[1]" and destination register "Q[1]"
    Info: fmax restricted to clock pin edge rate 2.222 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.593 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X37_Y7_N9; Fanout = 6; REG Node = 'Q[1]'
            Info: 2: + IC(0.314 ns) + CELL(0.376 ns) = 0.690 ns; Loc. = LCCOMB_X37_Y7_N14; Fanout = 3; COMB Node = 'WideNor0~11'
            Info: 3: + IC(0.243 ns) + CELL(0.660 ns) = 1.593 ns; Loc. = LCFF_X37_Y7_N9; Fanout = 6; REG Node = 'Q[1]'
            Info: Total cell delay = 1.036 ns ( 65.03 % )
            Info: Total interconnect delay = 0.557 ns ( 34.97 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "S1" to destination register is 3.570 ns
                Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_N23; Fanout = 1; CLK Node = 'S1'
                Info: 2: + IC(2.191 ns) + CELL(0.537 ns) = 3.570 ns; Loc. = LCFF_X37_Y7_N9; Fanout = 6; REG Node = 'Q[1]'
                Info: Total cell delay = 1.379 ns ( 38.63 % )
                Info: Total interconnect delay = 2.191 ns ( 61.37 % )
            Info: - Longest clock path from clock "S1" to source register is 3.570 ns
                Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_N23; Fanout = 1; CLK Node = 'S1'
                Info: 2: + IC(2.191 ns) + CELL(0.537 ns) = 3.570 ns; Loc. = LCFF_X37_Y7_N9; Fanout = 6; REG Node = 'Q[1]'
                Info: Total cell delay = 1.379 ns ( 38.63 % )
                Info: Total interconnect delay = 2.191 ns ( 61.37 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: Clock "S2" has Internal fmax of 313.09 MHz between source register "Q[2]" and destination register "Q[2]" (period= 3.194 ns)
    Info: + Longest register to register delay is 2.980 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X40_Y10_N9; Fanout = 6; REG Node = 'Q[2]'
        Info: 2: + IC(1.063 ns) + CELL(0.275 ns) = 1.338 ns; Loc. = LCCOMB_X37_Y7_N14; Fanout = 3; COMB Node = 'WideNor0~11'
        Info: 3: + IC(0.982 ns) + CELL(0.660 ns) = 2.980 ns; Loc. = LCFF_X40_Y10_N9; Fanout = 6; REG Node = 'Q[2]'
        Info: Total cell delay = 0.935 ns ( 31.38 % )
        Info: Total interconnect delay = 2.045 ns ( 68.62 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "S2" to destination register is 3.156 ns
            Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_P23; Fanout = 1; CLK Node = 'S2'
            Info: 2: + IC(1.777 ns) + CELL(0.537 ns) = 3.156 ns; Loc. = LCFF_X40_Y10_N9; Fanout = 6; REG Node = 'Q[2]'
            Info: Total cell delay = 1.379 ns ( 43.69 % )
            Info: Total interconnect delay = 1.777 ns ( 56.31 % )
        Info: - Longest clock path from clock "S2" to source register is 3.156 ns
            Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_P23; Fanout = 1; CLK Node = 'S2'
            Info: 2: + IC(1.777 ns) + CELL(0.537 ns) = 3.156 ns; Loc. = LCFF_X40_Y10_N9; Fanout = 6; REG Node = 'Q[2]'
            Info: Total cell delay = 1.379 ns ( 43.69 % )
            Info: Total interconnect delay = 1.777 ns ( 56.31 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: Clock "S3" Internal fmax is restricted to 450.05 MHz between source register "Q[3]" and destination register "Q[3]"
    Info: fmax restricted to clock pin edge rate 2.222 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.644 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X38_Y7_N31; Fanout = 6; REG Node = 'Q[3]'
            Info: 2: + IC(0.452 ns) + CELL(0.150 ns) = 0.602 ns; Loc. = LCCOMB_X37_Y7_N14; Fanout = 3; COMB Node = 'WideNor0~11'
            Info: 3: + IC(0.382 ns) + CELL(0.660 ns) = 1.644 ns; Loc. = LCFF_X38_Y7_N31; Fanout = 6; REG Node = 'Q[3]'
            Info: Total cell delay = 0.810 ns ( 49.27 % )
            Info: Total interconnect delay = 0.834 ns ( 50.73 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "S3" to destination register is 3.061 ns
                Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_W26; Fanout = 1; CLK Node = 'S3'
                Info: 2: + IC(1.662 ns) + CELL(0.537 ns) = 3.061 ns; Loc. = LCFF_X38_Y7_N31; Fanout = 6; REG Node = 'Q[3]'
                Info: Total cell delay = 1.399 ns ( 45.70 % )
                Info: Total interconnect delay = 1.662 ns ( 54.30 % )
            Info: - Longest clock path from clock "S3" to source register is 3.061 ns
                Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_W26; Fanout = 1; CLK Node = 'S3'
                Info: 2: + IC(1.662 ns) + CELL(0.537 ns) = 3.061 ns; Loc. = LCFF_X38_Y7_N31; Fanout = 6; REG Node = 'Q[3]'
                Info: Total cell delay = 1.399 ns ( 45.70 % )
                Info: Total interconnect delay = 1.662 ns ( 54.30 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "Q[2]" (data pin = "K", clock pin = "S2") is 6.211 ns
    Info: + Longest pin to register delay is 9.403 ns
        Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_H1; Fanout = 4; PIN Node = 'K'
        Info: 2: + IC(6.461 ns) + CELL(0.438 ns) = 7.761 ns; Loc. = LCCOMB_X37_Y7_N14; Fanout = 3; COMB Node = 'WideNor0~11'
        Info: 3: + IC(0.982 ns) + CELL(0.660 ns) = 9.403 ns; Loc. = LCFF_X40_Y10_N9; Fanout = 6; REG Node = 'Q[2]'
        Info: Total cell delay = 1.960 ns ( 20.84 % )
        Info: Total interconnect delay = 7.443 ns ( 79.16 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "S2" to destination register is 3.156 ns
        Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_P23; Fanout = 1; CLK Node = 'S2'
        Info: 2: + IC(1.777 ns) + CELL(0.537 ns) = 3.156 ns; Loc. = LCFF_X40_Y10_N9; Fanout = 6; REG Node = 'Q[2]'
        Info: Total cell delay = 1.379 ns ( 43.69 % )
        Info: Total interconnect delay = 1.777 ns ( 56.31 % )
Info: tco from clock "S1" to destination pin "HEX0[0]" through register "Q[1]" is 9.678 ns
    Info: + Longest clock path from clock "S1" to source register is 3.570 ns
        Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_N23; Fanout = 1; CLK Node = 'S1'
        Info: 2: + IC(2.191 ns) + CELL(0.537 ns) = 3.570 ns; Loc. = LCFF_X37_Y7_N9; Fanout = 6; REG Node = 'Q[1]'
        Info: Total cell delay = 1.379 ns ( 38.63 % )
        Info: Total interconnect delay = 2.191 ns ( 61.37 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 5.858 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X37_Y7_N9; Fanout = 6; REG Node = 'Q[1]'
        Info: 2: + IC(0.777 ns) + CELL(0.438 ns) = 1.215 ns; Loc. = LCCOMB_X37_Y7_N16; Fanout = 2; COMB Node = 'Decoder0~53'
        Info: 3: + IC(1.845 ns) + CELL(2.798 ns) = 5.858 ns; Loc. = PIN_AF10; Fanout = 0; PIN Node = 'HEX0[0]'
        Info: Total cell delay = 3.236 ns ( 55.24 % )
        Info: Total interconnect delay = 2.622 ns ( 44.76 % )
Info: th for register "Q[1]" (data pin = "K", clock pin = "S1") is -4.828 ns
    Info: + Longest clock path from clock "S1" to destination register is 3.570 ns
        Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_N23; Fanout = 1; CLK Node = 'S1'
        Info: 2: + IC(2.191 ns) + CELL(0.537 ns) = 3.570 ns; Loc. = LCFF_X37_Y7_N9; Fanout = 6; REG Node = 'Q[1]'
        Info: Total cell delay = 1.379 ns ( 38.63 % )
        Info: Total interconnect delay = 2.191 ns ( 61.37 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 8.664 ns
        Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_H1; Fanout = 4; PIN Node = 'K'
        Info: 2: + IC(6.461 ns) + CELL(0.438 ns) = 7.761 ns; Loc. = LCCOMB_X37_Y7_N14; Fanout = 3; COMB Node = 'WideNor0~11'
        Info: 3: + IC(0.243 ns) + CELL(0.660 ns) = 8.664 ns; Loc. = LCFF_X37_Y7_N9; Fanout = 6; REG Node = 'Q[1]'
        Info: Total cell delay = 1.960 ns ( 22.62 % )
        Info: Total interconnect delay = 6.704 ns ( 77.38 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 111 megabytes of memory during processing
    Info: Processing ended: Thu Oct 18 23:14:17 2007
    Info: Elapsed time: 00:00:02