jsq24_v.map.rpt

用verilog实现的记时器程序,在Quartus II上编译通过并成功运行

+---------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: CNT24:U4|lpm_divide:Mod0 ;
+------------------------+----------------+---------------------------------+
; Parameter Name         ; Value          ; Type                            ;
+------------------------+----------------+---------------------------------+
; LPM_WIDTHN             ; 8              ; Untyped                         ;
; LPM_WIDTHD             ; 4              ; Untyped                         ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                         ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                         ;
; LPM_PIPELINE           ; 0              ; Untyped                         ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                         ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                         ;
; CBXI_PARAMETER         ; lpm_divide_45m ; Untyped                         ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                         ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                         ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                  ;
+------------------------+----------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: CNT24:U4|lpm_divide:Div0 ;
+------------------------+----------------+---------------------------------+
; Parameter Name         ; Value          ; Type                            ;
+------------------------+----------------+---------------------------------+
; LPM_WIDTHN             ; 8              ; Untyped                         ;
; LPM_WIDTHD             ; 4              ; Untyped                         ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                         ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                         ;
; LPM_PIPELINE           ; 0              ; Untyped                         ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                         ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                         ;
; CBXI_PARAMETER         ; lpm_divide_1dm ; Untyped                         ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                         ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                         ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                  ;
+------------------------+----------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Oct 16 18:42:29 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off JSQ24_V -c JSQ24_V
Info: Found 1 design units, including 1 entities, in source file JSQ24_V.v
    Info: Found entity 1: JSQ24_V
Info: Elaborating entity "JSQ24_V" for the top level hierarchy
Warning: Using design file CLK_1HZ.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: CLK_1HZ
Info: Elaborating entity "CLK_1HZ" for hierarchy "CLK_1HZ:U1"
Warning (10230): Verilog HDL assignment warning at CLK_1HZ.v(8): truncated value with size 32 to match size of target (26)
Warning (10261): Verilog HDL Event Control warning at CNT60.v(7): Event Control contains a complex event expression
Warning: Using design file CNT60.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: CNT60
Info: Elaborating entity "CNT60" for hierarchy "CNT60:U2"
Warning (10230): Verilog HDL assignment warning at CNT60.v(11): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at CNT60.v(12): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at CNT60.v(13): truncated value with size 32 to match size of target (4)
Warning (10261): Verilog HDL Event Control warning at CNT24.v(7): Event Control contains a complex event expression
Warning: Using design file CNT24.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: CNT24
Info: Elaborating entity "CNT24" for hierarchy "CNT24:U4"
Warning (10230): Verilog HDL assignment warning at CNT24.v(11): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at CNT24.v(12): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at CNT24.v(13): truncated value with size 32 to match size of target (4)
Warning: Using design file dec7s.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: dec7s
Info: Elaborating entity "dec7s" for hierarchy "dec7s:U5"
Warning: Port "#0" on the entity instantiation of "U4" is connected to a signal of width 8. The formal width of the signal in the module is 1.  Extra bits will be driven by GND.
Warning: Port "#0" on the entity instantiation of "U3" is connected to a signal of width 8. The formal width of the signal in the module is 1.  Extra bits will be driven by GND.
Warning: Port "#4" on the entity instantiation of "U3" is connected to a signal of width 8. The formal width of the signal in the module is 1.  Extra bits will be left dangling without any fanout logic.
Warning: The following nets are missing source, defaulting to GND
    Warning: Net "X3[7]"
    Warning: Net "X3[6]"
    Warning: Net "X3[5]"
    Warning: Net "X3[4]"
    Warning: Net "X3[3]"
    Warning: Net "X3[2]"
    Warning: Net "X3[1]"
Warning: Port "#0" on the entity instantiation of "U2" is connected to a signal of width 8. The formal width of the signal in the module is 1.  Extra bits will be driven by GND.
Warning: Port "#4" on the entity instantiation of "U2" is connected to a signal of width 8. The formal width of the signal in the module is 1.  Extra bits will be left dangling without any fanout logic.
Warning: The following nets are missing source, defaulting to GND
    Warning: Net "X2[7]"
    Warning: Net "X2[6]"
    Warning: Net "X2[5]"
    Warning: Net "X2[4]"
    Warning: Net "X2[3]"
    Warning: Net "X2[2]"
    Warning: Net "X2[1]"
    Warning: Net "X3[7]"
    Warning: Net "X3[6]"
    Warning: Net "X3[5]"
    Warning: Net "X3[4]"
    Warning: Net "X3[3]"
    Warning: Net "X3[2]"
    Warning: Net "X3[1]"
Warning: Port "#1" on the entity instantiation of "U1" is connected to a signal of width 8. The formal width of the signal in the module is 1.  Extra bits will be left dangling without any fanout logic.
Warning: The following nets are missing source, defaulting to GND
    Warning: Net "X1[7]"
    Warning: Net "X1[6]"
    Warning: Net "X1[5]"
    Warning: Net "X1[4]"
    Warning: Net "X1[3]"
    Warning: Net "X1[2]"
    Warning: Net "X1[1]"
    Warning: Net "X2[7]"
    Warning: Net "X2[6]"
    Warning: Net "X2[5]"
    Warning: Net "X2[4]"
    Warning: Net "X2[3]"
    Warning: Net "X2[2]"
    Warning: Net "X2[1]"
    Warning: Net "X3[7]"
    Warning: Net "X3[6]"
    Warning: Net "X3[5]"
    Warning: Net "X3[4]"
    Warning: Net "X3[3]"
    Warning: Net "X3[2]"
    Warning: Net "X3[1]"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_divide.tdf
    Info: Found entity 1: lpm_divide
Info: Elaborated megafunction instantiation "CNT60:U2|lpm_divide:Mod0"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_45m.tdf
    Info: Found entity 1: lpm_divide_45m
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_bkh.tdf
    Info: Found entity 1: sign_div_unsign_bkh
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_ove.tdf
    Info: Found entity 1: alt_u_div_ove
Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf
    Info: Found entity 1: add_sub_lkc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf
    Info: Found entity 1: add_sub_mkc
Info: Elaborated megafunction instantiation "CNT60:U2|lpm_divide:Div0"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_1dm.tdf
    Info: Found entity 1: lpm_divide_1dm
Info: Implemented 571 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 43 output pins
    Info: Implemented 523 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 64 warnings
    Info: Processing ended: Tue Oct 16 18:42:33 2007
    Info: Elapsed time: 00:00:04