cnt60.tan.rpt

用verilog实现的记时器程序,在Quartus II上编译通过并成功运行

Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off CNT60 -c CNT60 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
    Info: Assuming node "js" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "always0~0" as buffer
Info: Clock "clk" has Internal fmax of 407.5 MHz between source register "q_temp[0]" and destination register "q_temp[4]" (period= 2.454 ns)
    Info: + Longest register to register delay is 2.240 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X51_Y28_N11; Fanout = 4; REG Node = 'q_temp[0]'
        Info: 2: + IC(0.343 ns) + CELL(0.414 ns) = 0.757 ns; Loc. = LCCOMB_X51_Y28_N10; Fanout = 2; COMB Node = 'Add0~97'
        Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.828 ns; Loc. = LCCOMB_X51_Y28_N12; Fanout = 2; COMB Node = 'Add0~99'
        Info: 4: + IC(0.000 ns) + CELL(0.159 ns) = 0.987 ns; Loc. = LCCOMB_X51_Y28_N14; Fanout = 2; COMB Node = 'Add0~101'
        Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.058 ns; Loc. = LCCOMB_X51_Y28_N16; Fanout = 2; COMB Node = 'Add0~103'
        Info: 6: + IC(0.000 ns) + CELL(0.410 ns) = 1.468 ns; Loc. = LCCOMB_X51_Y28_N18; Fanout = 1; COMB Node = 'Add0~104'
        Info: 7: + IC(0.268 ns) + CELL(0.420 ns) = 2.156 ns; Loc. = LCCOMB_X51_Y28_N0; Fanout = 1; COMB Node = 'q_temp~179'
        Info: 8: + IC(0.000 ns) + CELL(0.084 ns) = 2.240 ns; Loc. = LCFF_X51_Y28_N1; Fanout = 11; REG Node = 'q_temp[4]'
        Info: Total cell delay = 1.629 ns ( 72.72 % )
        Info: Total interconnect delay = 0.611 ns ( 27.28 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.955 ns
            Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.630 ns) + CELL(0.150 ns) = 1.759 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 1; COMB Node = 'always0~0'
            Info: 3: + IC(0.677 ns) + CELL(0.000 ns) = 2.436 ns; Loc. = CLKCTRL_G9; Fanout = 8; COMB Node = 'always0~0clkctrl'
            Info: 4: + IC(0.982 ns) + CELL(0.537 ns) = 3.955 ns; Loc. = LCFF_X51_Y28_N1; Fanout = 11; REG Node = 'q_temp[4]'
            Info: Total cell delay = 1.666 ns ( 42.12 % )
            Info: Total interconnect delay = 2.289 ns ( 57.88 % )
        Info: - Longest clock path from clock "clk" to source register is 3.955 ns
            Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.630 ns) + CELL(0.150 ns) = 1.759 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 1; COMB Node = 'always0~0'
            Info: 3: + IC(0.677 ns) + CELL(0.000 ns) = 2.436 ns; Loc. = CLKCTRL_G9; Fanout = 8; COMB Node = 'always0~0clkctrl'
            Info: 4: + IC(0.982 ns) + CELL(0.537 ns) = 3.955 ns; Loc. = LCFF_X51_Y28_N11; Fanout = 4; REG Node = 'q_temp[0]'
            Info: Total cell delay = 1.666 ns ( 42.12 % )
            Info: Total interconnect delay = 2.289 ns ( 57.88 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: Clock "js" has Internal fmax of 407.5 MHz between source register "q_temp[0]" and destination register "q_temp[4]" (period= 2.454 ns)
    Info: + Longest register to register delay is 2.240 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X51_Y28_N11; Fanout = 4; REG Node = 'q_temp[0]'
        Info: 2: + IC(0.343 ns) + CELL(0.414 ns) = 0.757 ns; Loc. = LCCOMB_X51_Y28_N10; Fanout = 2; COMB Node = 'Add0~97'
        Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.828 ns; Loc. = LCCOMB_X51_Y28_N12; Fanout = 2; COMB Node = 'Add0~99'
        Info: 4: + IC(0.000 ns) + CELL(0.159 ns) = 0.987 ns; Loc. = LCCOMB_X51_Y28_N14; Fanout = 2; COMB Node = 'Add0~101'
        Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.058 ns; Loc. = LCCOMB_X51_Y28_N16; Fanout = 2; COMB Node = 'Add0~103'
        Info: 6: + IC(0.000 ns) + CELL(0.410 ns) = 1.468 ns; Loc. = LCCOMB_X51_Y28_N18; Fanout = 1; COMB Node = 'Add0~104'
        Info: 7: + IC(0.268 ns) + CELL(0.420 ns) = 2.156 ns; Loc. = LCCOMB_X51_Y28_N0; Fanout = 1; COMB Node = 'q_temp~179'
        Info: 8: + IC(0.000 ns) + CELL(0.084 ns) = 2.240 ns; Loc. = LCFF_X51_Y28_N1; Fanout = 11; REG Node = 'q_temp[4]'
        Info: Total cell delay = 1.629 ns ( 72.72 % )
        Info: Total interconnect delay = 0.611 ns ( 27.28 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "js" to destination register is 4.059 ns
            Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 1; CLK Node = 'js'
            Info: 2: + IC(0.609 ns) + CELL(0.275 ns) = 1.863 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 1; COMB Node = 'always0~0'
            Info: 3: + IC(0.677 ns) + CELL(0.000 ns) = 2.540 ns; Loc. = CLKCTRL_G9; Fanout = 8; COMB Node = 'always0~0clkctrl'
            Info: 4: + IC(0.982 ns) + CELL(0.537 ns) = 4.059 ns; Loc. = LCFF_X51_Y28_N1; Fanout = 11; REG Node = 'q_temp[4]'
            Info: Total cell delay = 1.791 ns ( 44.12 % )
            Info: Total interconnect delay = 2.268 ns ( 55.88 % )
        Info: - Longest clock path from clock "js" to source register is 4.059 ns
            Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 1; CLK Node = 'js'
            Info: 2: + IC(0.609 ns) + CELL(0.275 ns) = 1.863 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 1; COMB Node = 'always0~0'
            Info: 3: + IC(0.677 ns) + CELL(0.000 ns) = 2.540 ns; Loc. = CLKCTRL_G9; Fanout = 8; COMB Node = 'always0~0clkctrl'
            Info: 4: + IC(0.982 ns) + CELL(0.537 ns) = 4.059 ns; Loc. = LCFF_X51_Y28_N11; Fanout = 4; REG Node = 'q_temp[0]'
            Info: Total cell delay = 1.791 ns ( 44.12 % )
            Info: Total interconnect delay = 2.268 ns ( 55.88 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "js" to destination pin "Q[4]" through register "q_temp[5]" is 21.086 ns
    Info: + Longest clock path from clock "js" to source register is 4.059 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 1; CLK Node = 'js'
        Info: 2: + IC(0.609 ns) + CELL(0.275 ns) = 1.863 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 1; COMB Node = 'always0~0'
        Info: 3: + IC(0.677 ns) + CELL(0.000 ns) = 2.540 ns; Loc. = CLKCTRL_G9; Fanout = 8; COMB Node = 'always0~0clkctrl'
        Info: 4: + IC(0.982 ns) + CELL(0.537 ns) = 4.059 ns; Loc. = LCFF_X51_Y28_N9; Fanout = 11; REG Node = 'q_temp[5]'
        Info: Total cell delay = 1.791 ns ( 44.12 % )
        Info: Total interconnect delay = 2.268 ns ( 55.88 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 16.777 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X51_Y28_N9; Fanout = 11; REG Node = 'q_temp[5]'
        Info: 2: + IC(0.544 ns) + CELL(0.393 ns) = 0.937 ns; Loc. = LCCOMB_X50_Y28_N6; Fanout = 2; COMB Node = 'lpm_divide:Div0|lpm_divide_1dm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_3_result_int[1]~11'
        Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 1.008 ns; Loc. = LCCOMB_X50_Y28_N8; Fanout = 2; COMB Node = 'lpm_divide:Div0|lpm_divide_1dm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_3_result_int[2]~13'
        Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.079 ns; Loc. = LCCOMB_X50_Y28_N10; Fanout = 1; COMB Node = 'lpm_divide:Div0|lpm_divide_1dm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_3_result_int[3]~15'
        Info: 5: + IC(0.000 ns) + CELL(0.410 ns) = 1.489 ns; Loc. = LCCOMB_X50_Y28_N12; Fanout = 10; COMB Node = 'lpm_divide:Div0|lpm_divide_1dm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_3_result_int[4]~16'
        Info: 6: + IC(0.981 ns) + CELL(0.275 ns) = 2.745 ns; Loc. = LCCOMB_X51_Y27_N4; Fanout = 2; COMB Node = 'lpm_divide:Div0|lpm_divide_1dm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|StageOut[16]~43'
        Info: 7: + IC(0.734 ns) + CELL(0.414 ns) = 3.893 ns; Loc. = LCCOMB_X51_Y29_N16; Fanout = 2; COMB Node = 'lpm_divide:Div0|lpm_divide_1dm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_4_result_int[2]~15'
        Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 3.964 ns; Loc. = LCCOMB_X51_Y29_N18; Fanout = 1; COMB Node = 'lpm_divide:Div0|lpm_divide_1dm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_4_result_int[3]~17'
        Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 4.035 ns; Loc. = LCCOMB_X51_Y29_N20; Fanout = 1; COMB Node = 'lpm_divide:Div0|lpm_divide_1dm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_4_result_int[4]~19'
        Info: 10: + IC(0.000 ns) + CELL(0.410 ns) = 4.445 ns; Loc. = LCCOMB_X51_Y29_N22; Fanout = 11; COMB Node = 'lpm_divide:Div0|lpm_divide_1dm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_4_result_int[5]~20'
        Info: 11: + IC(1.008 ns) + CELL(0.150 ns) = 5.603 ns; Loc. = LCCOMB_X50_Y28_N0; Fanout = 2; COMB Node = 'lpm_divide:Div0|lpm_divide_1dm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|StageOut[21]~33'
        Info: 12: + IC(0.779 ns) + CELL(0.414 ns) = 6.796 ns; Loc. = LCCOMB_X50_Y29_N10; Fanout = 2; COMB Node = 'lpm_divide:Div0|lpm_divide_1dm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_5_result_int[2]~15'
        Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 6.867 ns; Loc. = LCCOMB_X50_Y29_N12; Fanout = 1; COMB Node = 'lpm_divide:Div0|lpm_divide_1dm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_5_result_int[3]~17'
        Info: 14: + IC(0.000 ns) + CELL(0.159 ns) = 7.026 ns; Loc. = LCCOMB_X50_Y29_N14; Fanout = 1; COMB Node = 'lpm_divide:Div0|lpm_divide_1dm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_5_result_int[4]~19'
        Info: 15: + IC(0.000 ns) + CELL(0.410 ns) = 7.436 ns; Loc. = LCCOMB_X50_Y29_N16; Fanout = 11; COMB Node = 'lpm_divide:Div0|lpm_divide_1dm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_5_result_int[5]~20'
        Info: 16: + IC(0.487 ns) + CELL(0.415 ns) = 8.338 ns; Loc. = LCCOMB_X51_Y29_N2; Fanout = 3; COMB Node = 'lpm_divide:Div0|lpm_divide_1dm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|StageOut[27]~614'
        Info: 17: + IC(0.700 ns) + CELL(0.414 ns) = 9.452 ns; Loc. = LCCOMB_X49_Y29_N26; Fanout = 1; COMB Node = 'lpm_divide:Div0|lpm_divide_1dm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_6_result_int[3]~17'
        Info: 18: + IC(0.000 ns) + CELL(0.071 ns) = 9.523 ns; Loc. = LCCOMB_X49_Y29_N28; Fanout = 1; COMB Node = 'lpm_divide:Div0|lpm_divide_1dm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_6_result_int[4]~19'
        Info: 19: + IC(0.000 ns) + CELL(0.410 ns) = 9.933 ns; Loc. = LCCOMB_X49_Y29_N30; Fanout = 9; COMB Node = 'lpm_divide:Div0|lpm_divide_1dm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_6_result_int[5]~20'
        Info: 20: + IC(0.996 ns) + CELL(0.438 ns) = 11.367 ns; Loc. = LCCOMB_X48_Y28_N8; Fanout = 1; COMB Node = 'lpm_divide:Div0|lpm_divide_1dm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|StageOut[31]~13'
        Info: 21: + IC(0.722 ns) + CELL(0.414 ns) = 12.503 ns; Loc. = LCCOMB_X49_Y29_N6; Fanout = 1; COMB Node = 'lpm_divide:Div0|lpm_divide_1dm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_7_result_int[2]~15'
        Info: 22: + IC(0.000 ns) + CELL(0.071 ns) = 12.574 ns; Loc. = LCCOMB_X49_Y29_N8; Fanout = 1; COMB Node = 'lpm_divide:Div0|lpm_divide_1dm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_7_result_int[3]~17'
        Info: 23: + IC(0.000 ns) + CELL(0.071 ns) = 12.645 ns; Loc. = LCCOMB_X49_Y29_N10; Fanout = 1; COMB Node = 'lpm_divide:Div0|lpm_divide_1dm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_7_result_int[4]~19'
        Info: 24: + IC(0.000 ns) + CELL(0.410 ns) = 13.055 ns; Loc. = LCCOMB_X49_Y29_N12; Fanout = 1; COMB Node = 'lpm_divide:Div0|lpm_divide_1dm:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_ove:divider|add_sub_7_result_int[5]~20'
        Info: 25: + IC(0.944 ns) + CELL(2.778 ns) = 16.777 ns; Loc. = PIN_H17; Fanout = 0; PIN Node = 'Q[4]'
        Info: Total cell delay = 8.882 ns ( 52.94 % )
        Info: Total interconnect delay = 7.895 ns ( 47.06 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Tue Oct 16 16:56:57 2007
    Info: Elapsed time: 00:00:01