📄 cntreg.v
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module CNTREG(D,MODE,SEL,RD_,WR_,CLK,COUNTLSB,COUNTMSB,MODEWRITE,LOAD,OUTEN); input SEL, RD_, WR_, CLK, MODEWRITE; input [5:1] MODE; input [7:0] D; output LOAD, OUTEN; output [7:0] COUNTLSB, COUNTMSB; reg LOAD, OUTEN, LOADLSB, SETLOADLSB, CLRLOADLSB; reg [7:0] COUNTLSB, COUNTMSB; // Count Register always @(posedge WR_) if (SEL & RD_) case (MODE[5:4]) 'b01 : begin // Write LSB COUNTLSB = D; // Load Count On Next Rising CLK In Modes 0, 2, 3 and 4 if ((MODE[3:1] != 1) || (MODE[3:1] != 5)) LOAD = 'b1; // Enable Output OUTEN = 'b1; end 'b10 : begin // Write MSB COUNTMSB = D; // Load Count On Next Rising CLK In Modes 0, 2, 3 and 4 if ((MODE[3:1] != 1) || (MODE[3:1] != 5)) LOAD = 'b1; // Enable Output OUTEN = 'b1; end 'b11 : if (LOADLSB) begin // Write LSB First COUNTLSB = D; CLRLOADLSB = 'b1; end else begin // Write MSB Only After LSB Loaded COUNTMSB = D; SETLOADLSB = 'b1; // Load Count On Next Rising CLK In Modes 0, 2, 3 and 4 if ((MODE[3:1] != 1) || (MODE[3:1] != 5)) LOAD = 'b1; // Enable Output OUTEN = 'b1; end endcase always @(posedge CLK) LOAD = 'b0; // Flag LOADLSB Is Set When In 2 Byte Mode And LSB Has Not Been Read Yet always @(SETLOADLSB or MODEWRITE) if (SETLOADLSB || MODEWRITE) begin OUTEN = 'b0; LOADLSB = 'b1; COUNTLSB = 8'b0; COUNTMSB = 8'b0; end // Flag LOADLSB Is Cleared When In 2 Byte Mode And LSB Has Been Read always @(CLRLOADLSB) if (CLRLOADLSB) LOADLSB = 'b0;endmodule
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