modereg.v

来自「vcs tutorial lab1」· Verilog 代码 · 共 73 行

module MODEREG(D,MODE,SELMODE,RD_,WR_,MODEWRITE,SETOUT_,CLROUT_,MODETRIG,LATCHCNT);

  input        RD_,
               WR_,
               SELMODE;

  input  [7:0] D;

  output       SETOUT_,
               CLROUT_,
               MODETRIG,
               LATCHCNT,
               MODEWRITE;

  output [5:0] MODE;

  reg          SETOUT_,
               CLROUT_,
               MODETRIG,
               LATCHCNT,
               MODEWRITE;

  reg    [5:0] MODE; 
 
  // Mode Register

  always @(posedge WR_)
    if (SELMODE & RD_)
      begin

        // Write Mode Register

        MODE = D;

      end

  always @(SELMODE or RD_ or WR_)
    begin

      SETOUT_ = 'b1;
      CLROUT_ = 'b1;

      MODETRIG = 'b0;

      MODEWRITE = 'b0;

      if (SELMODE & RD_ & ~WR_)
        if (D[5:4])
           begin

             // Set Output High For All Modes Except 0

             if (D[3:1])
               SETOUT_ = 'b0;
             else
               CLROUT_ = 'b0;

             // Set Software Trigger In Mode 4

             if (D[3:1] == 4)
               MODETRIG = 'b1;

             MODEWRITE = 'b1;

           end
         else 
           LATCHCNT = 'b1;                      // Counter Latch Command

    end

endmodule