read.v

来自「vcs tutorial lab1」· Verilog 代码 · 共 99 行

module READ(D, LATCHLSB, LATCHMSB, MODE, SEL, RD_, WR_, MODEWRITE, CLRLATCH);

  input       SEL,
              RD_,
              WR_,
              MODEWRITE;
  input [5:4] MODE;
  input [7:0] D,
              LATCHLSB,
              LATCHMSB;

  output      CLRLATCH;

  reg         CLRLATCH,
              READLSB,
              SETREADLSB,
              CLRREADLSB;

  reg   [7:0] DREG;

  assign D = (SEL & ~RD_ & WR_) ? DREG : 8'bz;

  // Read Output Latch 

  always @(SEL or RD_ or WR_)
    if (SEL & ~RD_ & WR_)
      case (MODE[5:4])
        'b01 : begin
 
                 // Read LSB
 
                 assign DREG = LATCHLSB;

                 // Reset Latch Command

                 CLRLATCH = 'b1;
 
               end
        'b10 : begin
 
                 // Read MSB
 
                 assign DREG = LATCHMSB;
 
                 // Reset Latch Command
 
                 CLRLATCH = 'b1;
  
               end
        'b11 : if (READLSB)
                 begin
 
                   // Read LSB First
 
                   assign DREG = LATCHLSB;
                   CLRREADLSB = 'b1;
 
                 end
               else
                 begin
 
                   // Read MSB Only After LSB Is Read 
 
                   assign DREG = LATCHMSB;
                   SETREADLSB = 'b1;
 
                   // Reset Latch Command
 
                   CLRLATCH = 'b1;
  
                 end
      endcase
    else
      begin

        deassign DREG;

        CLRLATCH = 'b0;

        CLRREADLSB = 'b0;
        SETREADLSB = 'b0;

      end

  // Flag READLSB Is Set When In 2 Byte Mode And LSB Has Not Been Read Yet

  always @(SETREADLSB or MODEWRITE)
    if (SETREADLSB || MODEWRITE)
      READLSB = 'b1;

  // Flag READLSB Is Cleared When In 2 Byte Mode And LSB Has Been Read

  always @(CLRREADLSB)
    if (CLRREADLSB)
      READLSB = 'b0;

endmodule