c.v

来自「多发法定阿凡阿道夫埃罚罚 埃担罚大多发叮罚罚多发」· Verilog 代码 · 共 35 行

// dumping task are added after $monitor statement
module non_adder;
		parameter check = 1;
        
endmodule

module test_adder(out3,in1,in2);
   // test a 2 bit adder 
   parameter [1:0] par = 0;
   defparam par = 1;
   defparam test_adder.a.check = par + 1;
   input [1:0] in1,in2;
   wire[3:1] out;
   output [1:0] out3;
   time local_time;
   reg  [7:0] memo[0:255];
   event trigger;
   reg [1:0] test_reg;
   assign out = par? in1+in2 : 0;
   and test_and(out3[0],in1[0],in2);
   non_adder a();
   
   function show;
   	input [3:1] show_input1;
   	show = show_input1;
   endfunction
   initial
   begin
      test_reg = in1;
      local_time = $time;
   end
endmodule