c.v

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// Case/c.v 

module m(a,b,c,d,select,mux);
   input a,b,c,d;
   input [1:0] select;
   output mux;
   reg    mux;
 
   always@({a,b,c,d,select})
       case(select)
          2'b00: mux = a;
          default: mux = 'bx;
       endcase
   always@({a,b,c,d,select})
       casex(select)
          2'b00: mux = a;
          2'b1x: mux = d;
          default: mux = 'bx;
       endcase
   always@({a,b,c,d,select})
       casez(select)
          2'b00: mux = a;
          2'b1z: mux = d;
          default: mux = 'bx;
       endcase
endmodule