c.v

多发法定阿凡阿道夫埃罚罚 埃担罚大多发叮罚罚多发

module Assignment_test;
wire a1;
wire a2;
wire c;
reg b;
initial 
  begin 
    b = a1+a2;
    b <= a1-a2;
    b <= repeat(2) @(c) c;
    b <= #10 c;
    b = @(c) c;
  end
endmodule