c.v

多发法定阿凡阿道夫埃罚罚 埃担罚大多发叮罚罚多发

module test_adder(out);
   output[3:1] out;
   wire[3:1] out;
   //limitation: can not get the signal's connected port/portinst if part of the signal is used in port/portinst or the signal is used as part of port/portinst.
   //if the signal "out" is used as a whole port/portinst,connected port instance or port can be get without problem.
   //in this case,following port instances are also PrimTerm.
   and (out[1],in1,in2);
endmodule