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📄 fm.sim.vwf

📁 VHDL编写的驱动DDS
💻 VWF
📖 第 1 页 / 共 4 页
字号:
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1234 
TRANSITION_LIST("data_out[7]")
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}

TRANSITION_LIST("data_out[6]")
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		LEVEL 1 FOR 6400.0;
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}

TRANSITION_LIST("data_out[5]")
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}

TRANSITION_LIST("data_out[4]")
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TRANSITION_LIST("data_out[3]")
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TRANSITION_LIST("data_out[2]")
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}

TRANSITION_LIST("data_out[1]")
{
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		NODE
		{
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		NODE
		{
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		LEVEL 0 FOR 6400.0;
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}

TRANSITION_LIST("data_out[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 42387.725;
		LEVEL 1 FOR 3200.0;
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		LEVEL 1 FOR 3200.0;
		LEVEL 0 FOR 6400.0;
		LEVEL 1 FOR 6400.0;
		LEVEL 0 FOR 3200.0;
1234

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