div2.v

32位除法器 被除数和除数均为16位整数

/* ============================================================================
Author      : Li Chunyang
Date        : DEC. 2, 2007
File        : div2.v
Overview    : 
Reversion   : 3.0
Copyright   : COPYRIGHT (C) 2007 IMECAS 
                    ALL RIGHTS RESERVED
============================================================================ */

module div2(               // SRT division, radix-2
       dividend,           // dividend
       divisor,            // divisor
       quotient,           // quotient
       remainder,          // remainder{remainder,          // remainder}
       start,              // start=1,division begins to work, or it does not work
       clock,              // system clock, positive edge effect
       finish,             // finish=1,compution is finished
       error);             // error=1 while divisor=0

  parameter m=16;          // dot position
  parameter n=32;          // bit length
    
  input [n-1:0]    dividend;
  input [n-1:0]    divisor;
  input            start;
  input            clock;
  
  output [n+m-1:0]  quotient;
  output [n-1:0]    remainder;
  output            finish;
  output            error;
        
  reg [n+m-1:0]  quotient;
  reg [n-1:0]    remainder;
  
  reg            finish;
  reg            error;
  reg [5:0] width;         // a flag used to counter the number of the compution

  reg [2*n-1:0]  sub_dividend; // register to save dividend in the form of 64 bits
  reg [2*n-1:0]  sub_divisor;  // register to save divisor in the form of 64 bits
  reg [2:0]      state;        // state register

  parameter idle =3'b001,      // a state used to get ready for the process state
            process=3'b010,    // a state most of the calculation is finished 
            over=3'b100;       // calculation is finished, the data following is valid

  
  always@(posedge clock)    // system clock, positive edge effect
    if(!start)              // system initial when start==0
      begin
        error<=0;
        finish<=0;
        quotient<=0;
        remainder<=0;
      end
    else                   // initialization before data process
      begin
        sub_divisor[(2*n-1):(n)]<=divisor;
        sub_divisor[(n-1):0]<=32'b00000000000000000000000000000000;
        sub_dividend[(2*n-1):(n)]<=32'b00000000000000000000000000000000;
        sub_dividend[(n-1):0]<=dividend;
        width<=6'b110001;   // the number of total calculation
        case(state)
              idle: begin
                  if(divisor==0)     // to judge whether divisor==0,if it is,error happens
                    begin
                    error<=1;
                    state<=idle;
                    end
                  else begin
                      if(finish==1) begin   //to judge whether finish==1,if it is,calculation has finished
                      state<=idle;  end
                      else  begin
                      state<=process;      //divisor and finish valid, calculation begins
                      end
                  end
                end
              process:  begin
                  if(width==0)begin  //if width==0,calculation finished
                    state<=over;
                    end
                  else begin
                  sub_dividend<=sub_dividend<<1;       //sub_dividend shift left 1bit
                  if(sub_dividend[(2*n-1):n]>=sub_divisor[(2*n-1):n]) begin
                    quotient[width-1]<=1;                      
                    sub_dividend<=(sub_dividend-sub_divisor)<<1; 
                    remainder<=(sub_dividend[(2*n-1):n]);end
                  else begin                  //to judge every bit of quotient=0 or =1
                    quotient[width-1]<=0;
                    sub_dividend<=sub_dividend<<1;
                    remainder<=(sub_dividend[(2*n-1):n]); end
                  width<=width-1;
                  state<=process;
                  end
              end
               over: begin            //calculation is finished, finishe=1
                   finish<=1;
                   state<=idle;
                   end
             default: begin
                   state<=idle;
                   end
      endcase
  end
endmodule