psig.v

来自「FPGA verilog」· Verilog 代码 · 共 28 行

module PSig
	(
		CLK,
		Gain,
		InputPwr,
		Result
	);
	
	input			CLK;
	input	[31:0]	Gain;
	input	[23:0]	InputPwr;
	output	[31:0]	Result;

	reg		[31:0]	Result;

	wire	[55:0]	ResultTmp;
	
	lpm_mult_unsigned_24x32_hard	PsigCalc(
				.dataa(InputPwr),
				.datab(Gain),
				.result(ResultTmp));
	
	always @(posedge CLK)
	begin
		Result = ResultTmp[46:15];
	end
endmodule