adinput.v

来自「FPGA verilog」· Verilog 代码 · 共 79 行

module ADInput
	(
		AD_CLK,
		SYS_CLK,
		SYS_SAMP_CLK,
		InputPwrAD,
		OutputPwrAD,
		VOAInputAD,
		VOAOutputAD,
		RFLAD,
		InputPwrAD_Signal,
		OutputPwrAD_Signal,
		VOAInputAD_Signal,
		VOAOutputAD_Signal,
		RFLAD_Signal
	);
	
	input	AD_CLK;
	input	SYS_CLK;
	input	SYS_SAMP_CLK;
	input	[11:0]	InputPwrAD;
	input	[11:0]	OutputPwrAD;
	input	[11:0]	VOAInputAD;
	input	[11:0]	VOAOutputAD;
	input	[11:0]	RFLAD;
	output	[11:0]	InputPwrAD_Signal;
	output	[11:0]	OutputPwrAD_Signal;
	output	[11:0]	VOAInputAD_Signal;
	output	[11:0]	VOAOutputAD_Signal;
	output	[11:0]	RFLAD_Signal;

	reg		[11:0]	InputPwrAD_Signal;
	reg		[11:0]	OutputPwrAD_Signal;
	reg		[11:0]	VOAInputAD_Signal;
	reg		[11:0]	VOAOutputAD_Signal;
	reg		[11:0]	RFLAD_Signal;


	reg		[11:0]	InputPwrADReg;
	reg		[11:0]	OutputPwrADReg;
	reg		[11:0]	VOAInputADReg;
	reg		[11:0]	VOAOutputADReg;
	reg		[11:0]	RFLADReg;
	
	reg				Ad_SampReg;
	reg				SetReg;
	
	always @(posedge SYS_SAMP_CLK)
	begin
		if (AD_CLK)
			Ad_SampReg <= 1'b1;
		else if (Ad_SampReg)
		begin
			InputPwrADReg <= InputPwrAD;
			OutputPwrADReg<=OutputPwrAD;
			VOAInputADReg<=VOAInputAD;
			VOAOutputADReg<=VOAOutputAD;
			RFLADReg <= RFLAD;
			Ad_SampReg <= 1'b0;
		end
	end

	always @(posedge SYS_SAMP_CLK)
	begin
		if (SYS_CLK)
			SetReg <= 1'b1;
		else if (SetReg)
		begin	
			InputPwrAD_Signal <= InputPwrADReg;
			OutputPwrAD_Signal<=OutputPwrADReg;
			VOAInputAD_Signal<=VOAInputADReg;
			VOAOutputAD_Signal<=VOAOutputADReg;
			RFLAD_Signal<=RFLADReg;
			SetReg <= 1'b0;
		end
	end

endmodule