k_bcalculator.v

FPGA verilog

module K_BCalculator(
	B,
	K,
	X,
	result
);

input	[31:0] B;
input	[31:0] K;
input	[11:0] X;
output	[31:0] result;

wire	[43:0] 	wire1;

lpm_mult_unsigned_12x32_hard b2v_inst2(.dataa(X),.datab(K),.result(wire1));

lpm_add_signed_32	b2v_add2(.dataa(wire1[31:0]),
					.datab(B),
					.result(result));
endmodule