clock.v

来自「FPGA verilog」· Verilog 代码 · 共 31 行

module Clock(
	SYS_CLKIN0,
	SYS_CLKIN1,
	SYS_CLKIN2,
	PUMP_DAC_CLK,
	VOA_CLK,
	SYS_CLKOUT,
	SYS_SAMP_CLK
);

input	SYS_CLKIN0;
input	SYS_CLKIN1;
input	SYS_CLKIN2;
output	PUMP_DAC_CLK;
output	VOA_CLK;
output	SYS_CLKOUT;
output	SYS_SAMP_CLK;

altpll0	syspll(.inclk0(SYS_CLKIN0),
				.c0(SYS_SAMP_CLK),
				.c1(SYS_CLKOUT));

altpll1	pump0pll(.inclk0(SYS_CLKIN1),
				.c2(PUMP_DAC_CLK));
				
altpll1	voapll(.inclk0(SYS_CLKIN2),
				.c2(VOA_CLK));


endmodule