rflalarmmonitor.v

来自「FPGA verilog」· Verilog 代码 · 共 108 行

module RFLAlarmMonitor
	(
		EN,
		SYS_CLK,
		Param,
		PumpDown,		
		Debounce_Time_Set,
		THR_Set,
		HYS_Set,
		Alarm_Output
	);
	
	input 			EN;
	input 			SYS_CLK;
	input			PumpDown;
	input	[31:0]	Param,
					THR_Set,
					HYS_Set;
	input	[31:0]	Debounce_Time_Set;
	output 			Alarm_Output;
	
	reg 			AlarmReg;
	reg				Alarm;
	reg				ResumeAlarm;
	reg		[31:0]	RaiseTime,ResumeTime;
	wire	[31:0]	Hys;
	
	integer		iThr,
				iHys,
				iParam0,
				iParam1;

	lpm_add_signed_32 HysAdd(.dataa(THR_Set),
						.datab(HYS_Set),
						.result(Hys));
	
	assign Alarm_Output = AlarmReg;
	
	always @(Param or THR_Set)
	begin
		iParam0 = Param;
		iThr = THR_Set;
		if (iParam0<iThr)
			Alarm = 1'b1;
		else
			Alarm = 1'b0;
	end
	
	always @(Param or Hys)
	begin
		iParam1 = Param;
		iHys = Hys;
		if (iParam1>iHys)
			ResumeAlarm = 1'b1;
		else
			ResumeAlarm = 1'b0;
	end
	
	always @(posedge SYS_CLK)
	begin
		if (Alarm)
		begin
			if (RaiseTime[31]!=1)
				RaiseTime <= RaiseTime + 1'b1;
		end
		else if (ResumeTime>32'd2)
			RaiseTime <= 32'h00000000;
	end

	always @(posedge SYS_CLK)
	begin
		if (!Alarm)
		begin
			if (ResumeTime[31]!=1)
				ResumeTime <= ResumeTime + 1'b1;
		end
		else if (RaiseTime>32'd2)
			ResumeTime <= 32'h00000000;
	end
	
	always @(posedge SYS_CLK)
	begin
		if (EN)
		begin
			if (PumpDown)
			begin
				AlarmReg <= 1'b0;
			end
			else begin
				if (Alarm)
				begin
					if (RaiseTime>32'd1000)
						AlarmReg <= 1'b1;
				end
				else begin
					if (ResumeAlarm)
					begin
						if (ResumeTime>Debounce_Time_Set)
							AlarmReg <= 1'b0;
					end
				end
			end
		end
	end
		
endmodule