dop2alarmmonitor.v

来自「FPGA verilog」· Verilog 代码 · 共 46 行

module DOP2AlarmMonitor
	(
		EN,
		SYS_CLK,
		Ref,
		Param,
		Debounce_Time_Set,
		THR_Set,
		HYS_Set,
		Alarm_Output
	);
	
	input 			EN;
	input 			SYS_CLK;
	input	[31:0]	Ref;
	input	[31:0]	Param,
					THR_Set,
					HYS_Set;
	input	[31:0]	Debounce_Time_Set;
	output 			Alarm_Output;
	
	wire	[31:0]	THR_H_Set,THR_L_Set;
		
	lpm_sub_signed_32 Hyssub(.dataa(Ref),
						.datab(THR_Set),
						.result(THR_L_Set));

	lpm_add_signed_32 Hysadd(.dataa(Ref),
						.datab(THR_Set),
						.result(THR_H_Set));
	
	LTGT0AlarmMonitor TheAlarmMonitor(
				.EN(EN),
				.SYS_CLK(SYS_CLK),
				.Param(Param),
				.Debounce_Time_Set(Debounce_Time_Set),
				.THR_H_Set(THR_H_Set),
				.HYS_H_Set(HYS_Set),
				.THR_L_Set(THR_L_Set),
				.HYS_L_Set(HYS_Set),
				.Alarm_Output(Alarm_Output)
			);
	
endmodule