inputfilter.v

来自「FPGA verilog」· Verilog 代码 · 共 34 行

module InputFilter
	(
		CLK,
		KeyInput,
		KeyOutput
	);

	input	CLK;
	input	KeyInput;
	output	KeyOutput;
	
	reg		[3:0]	Counter;
	reg				Samp;
	
	assign  KeyOutput = Samp;
	
	always @(posedge CLK)
	begin
		if (Samp^KeyInput)
		begin
			if (Counter[3]==1'b1)//1us
			begin
				Counter <= 4'b0000;
				Samp <= KeyInput;
			end
			else
				Counter <= Counter + 1'b1;
		end
		else
			Counter <= 4'b0000;
	end
	
endmodule