dac.v

来自「FPGA verilog」· Verilog 代码 · 共 45 行

module DAC
(
	DAC_CLK,
	VOA_CLK,
	Pump_DacData, 
	VOA_DacData, 
	Pump_DacOut, 
	VOA_DacOut
);
	input 			DAC_CLK;
	input 			VOA_CLK;
	input 	[11:0] 	Pump_DacData,
					VOA_DacData;
					
	output 	[11:0] 	Pump_DacOut;
	output 	[11:0] 	VOA_DacOut;

	reg 	[11:0] 	Pump_DacOut;
	reg	 	[11:0] 	VOA_DacOut;

	reg		[11:0]	Q0,Q1;
	
	always @(negedge DAC_CLK)
	begin
		Q0 <= Pump_DacData;
	end

	always @(negedge VOA_CLK)
	begin
		Q1 <= VOA_DacData;
	end

	always @(negedge DAC_CLK)
	begin
		Pump_DacOut <= Q0;
	end

	always @(negedge VOA_CLK)
	begin
		VOA_DacOut <= Q1;
	end

endmodule