pwrfilter.v

FPGA verilog

module PwrFilter
	(
		CLK,
		InputData,
		OutputData
	);

	input				CLK;
	input	[31:0]		InputData;
	output	[31:0]		OutputData;
	

	reg		[31:0]		InputDataReg;
	reg		[31:0]		OutputData;
	reg		[38:0]		AccResult;
	wire	[38:0]		ParamResult;
	wire	[38:0]		Result;

	reg		[31:0] Input0,
             Input1,
             Input2,
             Input3,
             Input4,
             Input5,
             Input6,
             Input7,
             Input8,
             Input9,
             Input10,
             Input11,
             Input12,
             Input13,
             Input14,
             Input15,
             Input16,
             Input17,
             Input18,
             Input19,
             Input20,
             Input21,
             Input22,
             Input23,
             Input24,
             Input25,
             Input26,
             Input27,
             Input28,
             Input29,
             Input30,
             Input31,
             Input32,
             Input33,
             Input34,
             Input35,
             Input36,
             Input37,
             Input38,
             Input39,
             Input40,
             Input41,
             Input42,
             Input43,
             Input44,
             Input45,
             Input46,
             Input47,
             Input48,
             Input49,
             Input50,
             Input51,
             Input52,
             Input53,
             Input54,
             Input55,
             Input56,
             Input57,
             Input58,
             Input59,
             Input60,
             Input61,
             Input62,
             Input63,
             Input64,
             Input65,
             Input66,
             Input67,
             Input68,
             Input69,
             Input70,
             Input71,
             Input72,
             Input73,
             Input74,
             Input75,
             Input76,
             Input77,
             Input78,
             Input79,
             Input80,
             Input81,
             Input82,
             Input83,
             Input84,
             Input85,
             Input86,
             Input87,
             Input88,
             Input89,
             Input90,
             Input91,
             Input92,
             Input93,
             Input94,
             Input95,
             Input96,
             Input97,
             Input98,
             Input99,
             Input100,
             Input101,
             Input102,
             Input103,
             Input104,
             Input105,
             Input106,
             Input107,
             Input108,
             Input109,
             Input110,
             Input111,
             Input112,
             Input113,
             Input114,
             Input115,
             Input116,
             Input117,
             Input118,
             Input119,
             Input120,
             Input121,
             Input122,
             Input123,
             Input124,
             Input125,
             Input126,
             Input127;


	lpm_add_signed_39	ParamAcc(.dataa(AccResult),
							.datab(ParamResult),
							.result(Result));

	lpm_sub_signed_39	ParamSub(.dataa({7'b0000000,InputDataReg}),
							.datab({7'b0000000,Input127}),
							.result(ParamResult));
							
	
	always @(posedge CLK)
	begin
		InputDataReg <= InputData;
	end

	always @(posedge CLK)
	begin
		OutputData <= AccResult[38:7];
	end
	
	always @(posedge CLK)
	begin
		AccResult <= Result;
	end
	
	always @(posedge CLK)
	begin
		Input0 <= InputDataReg;
        Input1 <= Input0;
        Input2 <= Input1;
        Input3 <= Input2;
        Input4 <= Input3;
        Input5 <= Input4;
        Input6 <= Input5;
        Input7 <= Input6;
        Input8 <= Input7;
        Input9 <= Input8;
        Input10 <= Input9;
        Input11 <= Input10;
        Input12 <= Input11;
        Input13 <= Input12;
        Input14 <= Input13;
        Input15 <= Input14;
        Input16 <= Input15;
        Input17 <= Input16;
        Input18 <= Input17;
        Input19 <= Input18;
        Input20 <= Input19;
        Input21 <= Input20;
        Input22 <= Input21;
        Input23 <= Input22;
        Input24 <= Input23;
        Input25 <= Input24;
        Input26 <= Input25;
        Input27 <= Input26;
        Input28 <= Input27;
        Input29 <= Input28;
        Input30 <= Input29;
        Input31 <= Input30;
        Input32 <= Input31;
        Input33 <= Input32;
        Input34 <= Input33;
        Input35 <= Input34;
        Input36 <= Input35;
        Input37 <= Input36;
        Input38 <= Input37;
        Input39 <= Input38;
        Input40 <= Input39;
        Input41 <= Input40;
        Input42 <= Input41;
        Input43 <= Input42;
        Input44 <= Input43;
        Input45 <= Input44;
        Input46 <= Input45;
        Input47 <= Input46;
        Input48 <= Input47;
        Input49 <= Input48;
        Input50 <= Input49;
        Input51 <= Input50;
        Input52 <= Input51;
        Input53 <= Input52;
        Input54 <= Input53;
        Input55 <= Input54;
        Input56 <= Input55;
        Input57 <= Input56;
        Input58 <= Input57;
        Input59 <= Input58;
        Input60 <= Input59;
        Input61 <= Input60;
        Input62 <= Input61;
        Input63 <= Input62;
        Input64 <= Input63;
        Input65 <= Input64;
        Input66 <= Input65;
        Input67 <= Input66;
        Input68 <= Input67;
        Input69 <= Input68;
        Input70 <= Input69;
        Input71 <= Input70;
        Input72 <= Input71;
        Input73 <= Input72;
        Input74 <= Input73;
        Input75 <= Input74;
        Input76 <= Input75;
        Input77 <= Input76;
        Input78 <= Input77;
        Input79 <= Input78;
        Input80 <= Input79;
        Input81 <= Input80;
        Input82 <= Input81;
        Input83 <= Input82;
        Input84 <= Input83;
        Input85 <= Input84;
        Input86 <= Input85;
        Input87 <= Input86;
        Input88 <= Input87;
        Input89 <= Input88;
        Input90 <= Input89;
        Input91 <= Input90;
        Input92 <= Input91;
        Input93 <= Input92;
        Input94 <= Input93;
        Input95 <= Input94;
        Input96 <= Input95;
        Input97 <= Input96;
        Input98 <= Input97;
        Input99 <= Input98;
        Input100 <= Input99;
        Input101 <= Input100;
        Input102 <= Input101;
        Input103 <= Input102;
        Input104 <= Input103;
        Input105 <= Input104;
        Input106 <= Input105;
        Input107 <= Input106;
        Input108 <= Input107;
        Input109 <= Input108;
        Input110 <= Input109;
        Input111 <= Input110;
        Input112 <= Input111;
        Input113 <= Input112;
        Input114 <= Input113;
        Input115 <= Input114;
        Input116 <= Input115;
        Input117 <= Input116;
        Input118 <= Input117;
        Input119 <= Input118;
        Input120 <= Input119;
        Input121 <= Input120;
        Input122 <= Input121;
        Input123 <= Input122;
        Input124 <= Input123;
        Input125 <= Input124;
        Input126 <= Input125;
        Input127 <= Input126;
	end
	
endmodule