timer.rpt
来自「利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。」· RPT 代码 · 共 1,270 行 · 第 1/5 页
RPT
1,270 行
- 1 - C 06 DFFE 0 2 0 10 |DECODER_DYNAMIC:13|temp1 (|DECODER_DYNAMIC:13|:47)
- 1 - C 12 DFFE 0 1 0 11 |DECODER_DYNAMIC:13|temp0 (|DECODER_DYNAMIC:13|:48)
- 2 - C 10 AND2 0 3 0 5 |DECODER_DYNAMIC:13|:483
- 5 - C 13 OR2 ! 0 3 0 1 |DECODER_DYNAMIC:13|:486
- 1 - C 05 AND2 0 3 0 5 |DECODER_DYNAMIC:13|:493
- 1 - B 24 OR2 ! 0 3 0 1 |DECODER_DYNAMIC:13|:496
- 7 - C 05 OR2 ! 0 3 1 6 |DECODER_DYNAMIC:13|:503
- 4 - B 24 OR2 ! 0 3 0 1 |DECODER_DYNAMIC:13|:506
- 2 - C 05 OR2 ! 0 3 1 4 |DECODER_DYNAMIC:13|:513
- 4 - B 03 OR2 ! 0 3 0 1 |DECODER_DYNAMIC:13|:516
- 1 - C 07 OR2 ! 0 3 1 4 |DECODER_DYNAMIC:13|:523
- 6 - A 01 OR2 ! 0 3 0 1 |DECODER_DYNAMIC:13|:526
- 2 - C 09 OR2 ! 0 3 1 4 |DECODER_DYNAMIC:13|:533
- 4 - A 01 OR2 ! 0 3 0 1 |DECODER_DYNAMIC:13|:536
- 3 - C 09 OR2 ! 0 3 1 4 |DECODER_DYNAMIC:13|:543
- 1 - A 01 OR2 ! 0 3 0 9 |DECODER_DYNAMIC:13|:546
- 3 - C 24 OR2 ! 0 3 0 1 |DECODER_DYNAMIC:13|:552
- 3 - B 23 OR2 ! 0 3 0 1 |DECODER_DYNAMIC:13|:555
- 4 - B 23 OR2 ! 0 3 0 1 |DECODER_DYNAMIC:13|:558
- 5 - B 03 OR2 ! 0 3 0 1 |DECODER_DYNAMIC:13|:561
- 3 - A 01 OR2 ! 0 3 0 1 |DECODER_DYNAMIC:13|:564
- 5 - A 01 OR2 ! 0 3 0 1 |DECODER_DYNAMIC:13|:567
- 2 - A 01 OR2 ! 0 3 0 9 |DECODER_DYNAMIC:13|:570
- 3 - C 16 OR2 0 3 0 1 |DECODER_DYNAMIC:13|:576
- 6 - B 23 OR2 0 3 0 1 |DECODER_DYNAMIC:13|:579
- 1 - B 23 OR2 0 3 0 1 |DECODER_DYNAMIC:13|:582
- 6 - B 10 OR2 0 3 0 1 |DECODER_DYNAMIC:13|:585
- 6 - A 04 OR2 0 3 0 1 |DECODER_DYNAMIC:13|:588
- 5 - A 04 OR2 0 3 0 1 |DECODER_DYNAMIC:13|:591
- 1 - A 04 OR2 0 3 0 16 |DECODER_DYNAMIC:13|:594
- 7 - C 19 OR2 0 3 0 1 |DECODER_DYNAMIC:13|:600
- 5 - B 23 OR2 0 3 0 1 |DECODER_DYNAMIC:13|:603
- 2 - B 23 OR2 0 3 0 1 |DECODER_DYNAMIC:13|:606
- 2 - B 10 OR2 0 3 0 1 |DECODER_DYNAMIC:13|:609
- 4 - A 04 OR2 0 3 0 1 |DECODER_DYNAMIC:13|:612
- 2 - A 04 OR2 0 3 0 1 |DECODER_DYNAMIC:13|:615
- 3 - A 04 OR2 0 3 0 13 |DECODER_DYNAMIC:13|:618
- 5 - C 05 AND2 0 4 1 0 |DECODER_DYNAMIC:13|:764
- 3 - C 05 AND2 0 3 1 0 |DECODER_DYNAMIC:13|:788
- 1 - C 09 AND2 0 3 1 0 |DECODER_DYNAMIC:13|:812
- 1 - B 11 AND2 s 0 2 0 3 |DECODER:2|~251~1
- 1 - B 02 OR2 ! 0 4 0 5 |DECODER:2|:263
- 2 - B 01 AND2 0 4 0 3 |DECODER:2|:275
- 8 - B 01 AND2 s 0 3 0 1 |DECODER:2|~287~1
- 1 - B 04 AND2 s 0 2 0 3 |DECODER:2|~290~1
- 2 - B 08 OR2 s 0 3 0 3 |DECODER:2|~290~2
- 8 - B 06 AND2 0 4 0 3 |DECODER:2|:299
- 6 - B 06 OR2 0 4 0 1 |DECODER:2|:316
- 3 - B 12 OR2 s 0 2 0 6 |DECODER:2|~335~1
- 7 - B 06 OR2 0 4 1 1 |DECODER:2|:350
- 3 - B 07 OR2 s 0 4 0 1 |DECODER:2|~383~1
- 6 - B 07 OR2 0 3 1 0 |DECODER:2|:383
- 7 - B 01 OR2 s ! 0 4 0 2 |DECODER:2|~407~1
- 6 - B 01 OR2 0 4 0 1 |DECODER:2|:407
- 4 - B 01 OR2 0 4 1 1 |DECODER:2|:416
- 5 - B 06 OR2 0 3 0 1 |DECODER:2|:433
- 3 - B 06 OR2 0 3 0 1 |DECODER:2|:442
- 1 - B 06 OR2 0 4 1 1 |DECODER:2|:449
- 1 - B 01 OR2 0 4 0 1 |DECODER:2|:458
- 5 - B 01 OR2 0 4 0 1 |DECODER:2|:478
- 1 - B 12 OR2 0 4 1 1 |DECODER:2|:482
- 2 - B 06 OR2 0 3 0 1 |DECODER:2|:499
- 3 - B 01 OR2 s 0 3 0 4 |DECODER:2|~503~1
- 4 - B 06 OR2 0 3 0 1 |DECODER:2|:503
- 7 - A 11 OR2 0 4 1 1 |DECODER:2|:515
- 1 - B 07 OR2 s 0 4 0 1 |DECODER:2|~542~1
- 2 - B 07 OR2 0 4 0 1 |DECODER:2|:542
- 5 - A 11 OR2 0 3 1 1 |DECODER:2|:548
- 1 - A 02 DFFE 1 1 0 35 |D_FF:18|:6
- 1 - A 20 DFFE 1 1 0 10 |D_FF:18|:8
- 4 - C 14 DFFE 1 1 0 3 |D_FF:18|:10
- 3 - C 21 DFFE 1 1 0 3 |D_FF:18|:12
- 2 - C 08 DFFE 0 2 0 5 |FRE_20:5|:2
- 6 - C 08 DFFE 0 4 0 1 |FRE_20:5|a3 (|FRE_20:5|:4)
- 1 - C 08 DFFE 0 4 0 2 |FRE_20:5|a2 (|FRE_20:5|:5)
- 3 - C 08 DFFE 0 3 0 3 |FRE_20:5|a1 (|FRE_20:5|:6)
- 4 - C 08 DFFE 0 2 0 4 |FRE_20:5|a0 (|FRE_20:5|:7)
- 5 - C 08 OR2 0 4 0 4 |FRE_20:5|:25
- 3 - C 04 AND2 0 2 0 1 |FRE_100:4|LPM_ADD_SUB:99|addcore:adder|:63
- 2 - C 04 AND2 0 4 0 2 |FRE_100:4|LPM_ADD_SUB:99|addcore:adder|:71
- 2 - C 07 DFFE 0 4 0 8 |FRE_100:4|:2
- 5 - C 07 DFFE 0 4 0 3 |FRE_100:4|a5 (|FRE_100:4|:4)
- 4 - C 07 DFFE 0 4 0 3 |FRE_100:4|a4 (|FRE_100:4|:5)
- 5 - C 04 DFFE 0 4 0 2 |FRE_100:4|a3 (|FRE_100:4|:6)
- 4 - C 04 DFFE 0 4 0 3 |FRE_100:4|a2 (|FRE_100:4|:7)
- 6 - C 04 DFFE 0 3 0 4 |FRE_100:4|a1 (|FRE_100:4|:8)
- 7 - C 04 DFFE 0 2 0 4 |FRE_100:4|a0 (|FRE_100:4|:9)
- 3 - C 07 OR2 0 3 0 4 |FRE_100:4|:35
- 1 - C 04 AND2 0 3 0 4 |FRE_100:4|:42
- 2 - C 23 AND2 0 2 0 1 |FRE_100:8|LPM_ADD_SUB:99|addcore:adder|:63
- 1 - C 23 AND2 0 4 0 2 |FRE_100:8|LPM_ADD_SUB:99|addcore:adder|:71
- 1 - C 11 DFFE + 0 3 0 7 |FRE_100:8|:2
- 2 - C 11 DFFE + 0 3 0 3 |FRE_100:8|a5 (|FRE_100:8|:4)
- 4 - C 11 DFFE + 0 3 0 3 |FRE_100:8|a4 (|FRE_100:8|:5)
- 4 - C 23 DFFE + 0 3 0 2 |FRE_100:8|a3 (|FRE_100:8|:6)
- 5 - C 23 DFFE + 0 3 0 3 |FRE_100:8|a2 (|FRE_100:8|:7)
- 7 - C 23 DFFE + 0 2 0 4 |FRE_100:8|a1 (|FRE_100:8|:8)
- 6 - C 23 DFFE + 0 1 0 4 |FRE_100:8|a0 (|FRE_100:8|:9)
- 3 - C 11 OR2 0 3 0 4 |FRE_100:8|:35
- 3 - C 23 AND2 0 3 0 4 |FRE_100:8|:42
- 3 - A 16 AND2 0 2 0 4 |HOUR:17|LPM_ADD_SUB:185|addcore:adder|:55
- 5 - A 16 OR2 0 3 0 1 |HOUR:17|LPM_ADD_SUB:185|addcore:adder|:69
- 2 - A 21 AND2 0 2 0 1 |HOUR:17|LPM_ADD_SUB:262|addcore:adder|:55
- 3 - A 21 AND2 0 3 0 1 |HOUR:17|LPM_ADD_SUB:262|addcore:adder|:59
- 1 - A 21 DFFE 0 5 0 3 |HOUR:17|:7
- 4 - A 21 DFFE 0 5 0 5 |HOUR:17|:9
- 6 - A 22 DFFE 0 4 0 7 |HOUR:17|:11
- 4 - A 14 DFFE 0 5 0 6 |HOUR:17|:13
- 4 - A 16 DFFE 0 6 0 6 |HOUR:17|:15
- 2 - A 16 DFFE 0 5 0 7 |HOUR:17|:17
- 2 - A 19 DFFE 0 5 0 6 |HOUR:17|:19
- 3 - A 22 DFFE 0 5 0 7 |HOUR:17|:21
- 7 - A 19 OR2 s 0 3 0 1 |HOUR:17|~122~1
- 1 - A 19 OR2 ! 0 3 0 2 |HOUR:17|:122
- 3 - A 18 OR2 s ! 0 4 0 2 |HOUR:17|~141~1
- 4 - A 19 OR2 ! 0 4 0 3 |HOUR:17|:141
- 8 - A 19 OR2 s 0 2 0 2 |HOUR:17|~160~1
- 7 - A 24 OR2 ! 0 4 0 6 |HOUR:17|:237
- 5 - A 21 OR2 s 0 3 0 2 |HOUR:17|~462~1
- 1 - A 22 AND2 s 0 2 0 4 |HOUR:17|~464~1
- 5 - A 22 OR2 0 3 0 1 |HOUR:17|:476
- 7 - A 22 OR2 0 4 0 1 |HOUR:17|:480
- 6 - A 16 OR2 0 4 0 1 |HOUR:17|:507
- 7 - A 16 OR2 0 4 0 1 |HOUR:17|:516
- 8 - A 16 OR2 0 4 0 1 |HOUR:17|:536
- 1 - A 16 OR2 0 4 0 1 |HOUR:17|:539
- 3 - A 19 OR2 0 4 0 1 |HOUR:17|:554
- 5 - A 19 OR2 s 0 4 0 3 |HOUR:17|~556~1
- 6 - A 19 OR2 0 4 0 1 |HOUR:17|:557
- 2 - A 22 AND2 s 0 2 0 3 |HOUR:17|~572~1
- 4 - A 22 OR2 0 4 0 1 |HOUR:17|:572
- 3 - C 20 AND2 0 3 0 1 |MMS:6|LPM_ADD_SUB:186|addcore:adder|:59
- 4 - C 22 AND2 0 3 0 1 |MMS:6|LPM_ADD_SUB:215|addcore:adder|:59
- 5 - C 22 OR2 0 2 0 1 |MMS:6|LPM_ADD_SUB:215|addcore:adder|:67
- 6 - C 22 OR2 0 3 0 1 |MMS:6|LPM_ADD_SUB:215|addcore:adder|:68
- 6 - C 19 DFFE 0 4 0 1 |MMS:6|:3
- 1 - C 22 DFFE 0 5 0 3 |MMS:6|:5
- 3 - C 22 DFFE 0 6 0 5 |MMS:6|:7
- 2 - C 22 DFFE 0 6 0 6 |MMS:6|:9
- 3 - C 15 DFFE 0 2 0 6 |MMS:6|:11
- 2 - C 20 DFFE 0 5 0 3 |MMS:6|:13
- 1 - C 17 DFFE 0 5 0 5 |MMS:6|:15
- 4 - C 20 DFFE 0 5 0 4 |MMS:6|:17
- 1 - C 13 DFFE 0 5 0 5 |MMS:6|:19
- 4 - C 17 OR2 s ! 0 2 0 2 |MMS:6|~96~1
- 6 - C 17 OR2 ! 0 4 0 6 |MMS:6|:96
- 3 - C 17 OR2 s 0 4 0 1 |MMS:6|~115~1
- 8 - C 17 OR2 ! 0 4 0 7 |MMS:6|:115
- 1 - C 24 OR2 ! 0 4 0 8 |MMS:6|:120
- 2 - C 17 OR2 s 0 4 0 1 |MMS:6|~314~1
- 1 - C 20 AND2 s 0 2 0 2 |MMS:6|~331~1
- 1 - B 18 AND2 0 2 0 4 |SEC:10|LPM_ADD_SUB:189|addcore:adder|:55
- 8 - B 15 OR2 0 2 0 1 |SEC:10|LPM_ADD_SUB:189|addcore:adder|:67
- 8 - B 20 OR2 0 3 0 1 |SEC:10|LPM_ADD_SUB:189|addcore:adder|:69
- 3 - B 24 AND2 0 2 0 1 |SEC:10|LPM_ADD_SUB:266|addcore:adder|:55
- 6 - B 24 AND2 0 3 0 1 |SEC:10|LPM_ADD_SUB:266|addcore:adder|:59
- 5 - B 17 DFFE 0 3 0 1 |SEC:10|:5
- 7 - B 24 DFFE 0 5 0 2 |SEC:10|:7
- 5 - B 24 DFFE 0 5 0 3 |SEC:10|:9
- 2 - B 16 DFFE 0 5 0 4 |SEC:10|:11
- 1 - B 21 DFFE 0 3 0 5 |SEC:10|:13
- 3 - B 20 DFFE 0 6 0 7 |SEC:10|:15
- 2 - B 20 DFFE 0 5 0 8 |SEC:10|:17
- 3 - B 15 DFFE 0 6 0 7 |SEC:10|:19
- 2 - B 15 DFFE 0 5 0 7 |SEC:10|:21
- 7 - B 17 OR2 s ! 0 2 0 2 |SEC:10|~126~1
- 4 - B 17 OR2 ! 0 4 0 6 |SEC:10|:126
- 6 - B 17 OR2 s 0 3 0 1 |SEC:10|~145~1
- 2 - B 17 OR2 ! 0 3 0 4 |SEC:10|:145
- 2 - B 24 OR2 ! 0 4 0 10 |SEC:10|:241
- 1 - B 17 OR2 s 0 4 0 1 |SEC:10|~449~1
- 1 - B 20 OR2 0 4 0 1 |SEC:10|:527
- 4 - B 20 OR2 0 4 0 1 |SEC:10|:536
- 5 - B 20 AND2 s 0 3 0 2 |SEC:10|~538~1
- 6 - B 20 OR2 0 4 0 1 |SEC:10|:556
- 7 - B 20 OR2 0 4 0 1 |SEC:10|:559
- 1 - B 15 OR2 0 4 0 1 |SEC:10|:566
- 4 - B 15 OR2 0 4 0 1 |SEC:10|:572
- 3 - B 17 OR2 s 0 4 0 3 |SEC:10|~576~1
- 5 - B 15 OR2 s 0 4 0 1 |SEC:10|~593~1
- 6 - B 15 OR2 s 0 4 0 1 |SEC:10|~593~2
- 5 - A 06 AND2 0 2 0 4 |SEC:24|LPM_ADD_SUB:189|addcore:adder|:55
- 7 - A 12 OR2 0 2 0 1 |SEC:24|LPM_ADD_SUB:189|addcore:adder|:67
- 8 - A 10 OR2 0 3 0 1 |SEC:24|LPM_ADD_SUB:189|addcore:adder|:69
- 7 - B 03 AND2 0 2 0 1 |SEC:24|LPM_ADD_SUB:266|addcore:adder|:55
- 8 - B 03 AND2 0 3 0 1 |SEC:24|LPM_ADD_SUB:266|addcore:adder|:59
- 5 - A 08 DFFE 0 3 0 1 |SEC:24|:5
- 6 - B 03 DFFE 0 5 0 2 |SEC:24|:7
- 3 - B 03 DFFE 0 5 0 3 |SEC:24|:9
- 2 - B 03 DFFE 0 5 0 4 |SEC:24|:11
- 4 - B 10 DFFE 0 3 0 5 |SEC:24|:13
- 2 - A 10 DFFE 0 6 0 7 |SEC:24|:15
- 7 - A 10 DFFE 0 5 0 8 |SEC:24|:17
- 2 - A 12 DFFE 0 6 0 7 |SEC:24|:19
- 1 - A 12 DFFE 0 5 0 7 |SEC:24|:21
- 4 - A 08 OR2 s ! 0 2 0 2 |SEC:24|~126~1
- 1 - A 08 OR2 ! 0 4 0 6 |SEC:24|:126
- 6 - A 08 OR2 s 0 3 0 1 |SEC:24|~145~1
- 2 - A 08 OR2 ! 0 3 0 4 |SEC:24|:145
- 1 - B 03 OR2 ! 0 4 0 10 |SEC:24|:241
- 7 - A 08 OR2 s 0 4 0 1 |SEC:24|~449~1
- 3 - A 10 OR2 0 4 0 1 |SEC:24|:527
- 4 - A 10 OR2 0 4 0 1 |SEC:24|:536
- 5 - A 10 AND2 s 0 3 0 2 |SEC:24|~538~1
- 6 - A 10 OR2 0 4 0 1 |SEC:24|:556
- 1 - A 10 OR2 0 4 0 1 |SEC:24|:559
- 3 - A 12 OR2 0 4 0 1 |SEC:24|:566
- 4 - A 12 OR2 0 4 0 1 |SEC:24|:572
- 3 - A 08 OR2 s 0 4 0 3 |SEC:24|~576~1
- 5 - A 12 OR2 s 0 4 0 1 |SEC:24|~593~1
- 6 - A 12 OR2 s 0 4 0 1 |SEC:24|~593~2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\eda\timer\timer.rpt
timer
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 15/ 96( 15%) 23/ 48( 47%) 15/ 48( 31%) 2/16( 12%) 2/16( 12%) 0/16( 0%)
B: 9/ 96( 9%) 21/ 48( 43%) 25/ 48( 52%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 7/ 96( 7%) 12/ 48( 25%) 20/ 48( 41%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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