decoder_dynamic.rpt
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RPT
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Project Information e:\kai\timer\decoder_dynamic.rpt
MAX+plus II Compiler Report File
Version 9.23 3/19/99
Compiled: 04/28/2007 20:53:33
Copyright (C) 1988-1999 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
DECODER_DYNAMIC
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
decoder_dynamic
EPM7064LC68-7 33 12 0 19 12 29 %
User Pins: 33 12 0
Project Information e:\kai\timer\decoder_dynamic.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information e:\kai\timer\decoder_dynamic.rpt
** FILE HIERARCHY **
|lpm_add_sub:81|
|lpm_add_sub:81|addcore:adder|
|lpm_add_sub:81|addcore:adder|addcore:adder0|
|lpm_add_sub:81|altshift:result_ext_latency_ffs|
|lpm_add_sub:81|altshift:carry_ext_latency_ffs|
|lpm_add_sub:81|altshift:oflow_ext_latency_ffs|
Device-Specific Information: e:\kai\timer\decoder_dynamic.rpt
decoder_dynamic
***** Logic for device 'decoder_dynamic' compiled without errors.
Device: EPM7064LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
Device-Specific Information: e:\kai\timer\decoder_dynamic.rpt
decoder_dynamic
** ERROR SUMMARY **
Info: Chip 'decoder_dynamic' in device 'EPM7064LC68-7' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
V
C V
C s s C s s
x s s G s s I G G G c G e e C e e
0 1 1 N 1 1 N N N N l N l l I l l
0 3 2 D 1 0 T D D D k D 3 2 O 1 0
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
x01 | 10 60 | q3
VCCIO | 11 59 | sel6
x02 | 12 58 | GND
x03 | 13 57 | q2
x10 | 14 56 | q1
x11 | 15 55 | q0
GND | 16 54 | sel5
x12 | 17 53 | VCCIO
x13 | 18 EPM7064LC68-7 52 | sel7
h11 | 19 51 | sel4
h02 | 20 50 | m11
VCCIO | 21 49 | RESERVED
h03 | 22 48 | GND
h00 | 23 47 | m03
m13 | 24 46 | m10
h10 | 25 45 | RESERVED
GND | 26 44 | RESERVED
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
m s s s V s m G V h h G R h m m V
0 0 0 0 C 0 1 N C 1 0 N E 1 0 0 C
2 0 1 2 C 3 2 D C 2 1 D S 3 0 1 C
I I E I
O N R O
T V
E
D
N.C. = No Connect, This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\kai\timer\decoder_dynamic.rpt
decoder_dynamic
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 12/12(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 0/16( 0%) 12/12(100%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 3/16( 18%) 8/12( 66%) 3/16( 18%) 18/36( 50%)
D: LC49 - LC64 16/16(100%) 12/12(100%) 13/16( 81%) 24/36( 66%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 44/48 ( 91%)
Total logic cells used: 19/64 ( 29%)
Total shareable expanders used: 12/64 ( 18%)
Total Turbo logic cells used: 19/64 ( 29%)
Total shareable expanders not available (n/a): 4/64 ( 6%)
Average fan-in: 4.89
Total fan-in: 93
Total input pins required: 33
Total output pins required: 12
Total bidirectional pins required: 0
Total logic cells required: 19
Total flipflops required: 3
Total product terms required: 47
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 12
Synthesized logic cells: 4/ 64 ( 6%)
Device-Specific Information: e:\kai\timer\decoder_dynamic.rpt
decoder_dynamic
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
67 - - INPUT G 0 0 0 0 0 0 0 clk
23 (28) (B) INPUT 0 0 0 0 0 0 1 h00
37 (35) (C) INPUT 0 0 0 0 0 0 1 h01
20 (30) (B) INPUT 0 0 0 0 0 0 1 h02
22 (29) (B) INPUT 0 0 0 0 0 0 1 h03
25 (25) (B) INPUT 0 0 0 0 0 1 0 h10
19 (32) (B) INPUT 0 0 0 0 0 1 0 h11
36 (33) (C) INPUT 0 0 0 0 0 1 0 h12
40 (37) (C) INPUT 0 0 0 0 0 1 0 h13
41 (38) (C) INPUT 0 0 0 0 0 0 1 m00
42 (40) (C) INPUT 0 0 0 0 0 0 1 m01
27 (24) (B) INPUT 0 0 0 0 0 0 1 m02
47 (45) (C) INPUT 0 0 0 0 0 0 1 m03
46 (44) (C) INPUT 0 0 0 0 0 1 0 m10
50 (48) (C) INPUT 0 0 0 0 0 1 0 m11
33 (17) (B) INPUT 0 0 0 0 0 1 0 m12
24 (27) (B) INPUT 0 0 0 0 0 1 0 m13
28 (22) (B) INPUT 0 0 0 0 0 0 1 s00
29 (21) (B) INPUT 0 0 0 0 0 0 1 s01
30 (20) (B) INPUT 0 0 0 0 0 0 1 s02
32 (19) (B) INPUT 0 0 0 0 0 0 1 s03
4 (16) (A) INPUT 0 0 0 0 0 1 0 s10
5 (14) (A) INPUT 0 0 0 0 0 1 0 s11
7 (13) (A) INPUT 0 0 0 0 0 1 0 s12
8 (12) (A) INPUT 0 0 0 0 0 1 0 s13
9 (11) (A) INPUT 0 0 0 0 0 0 1 x00
10 (9) (A) INPUT 0 0 0 0 0 0 1 x01
12 (8) (A) INPUT 0 0 0 0 0 0 1 x02
13 (6) (A) INPUT 0 0 0 0 0 0 1 x03
14 (5) (A) INPUT 0 0 0 0 0 0 1 x10
15 (4) (A) INPUT 0 0 0 0 0 0 1 x11
17 (3) (A) INPUT 0 0 0 0 0 0 1 x12
18 (1) (A) INPUT 0 0 0 0 0 0 1 x13
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\kai\timer\decoder_dynamic.rpt
decoder_dynamic
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
55 53 D OUTPUT t 3 0 0 3 4 0 0 q0
56 54 D OUTPUT t 3 0 0 3 4 0 0 q1
57 56 D OUTPUT t 3 0 0 3 4 0 0 q2
60 59 D OUTPUT t 3 0 0 3 4 0 0 q3
61 60 D OUTPUT t 0 0 0 0 3 0 0 sel0
62 61 D OUTPUT t 0 0 0 0 3 0 0 sel1
64 62 D OUTPUT t 0 0 0 0 3 0 0 sel2
65 64 D OUTPUT t 0 0 0 0 3 0 0 sel3
51 49 D OUTPUT t 0 0 0 0 3 0 0 sel4
54 52 D OUTPUT t 0 0 0 0 3 0 0 sel5
59 57 D OUTPUT t 0 0 0 0 3 0 0 sel6
52 51 D OUTPUT t 0 0 0 0 3 0 0 sel7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\kai\timer\decoder_dynamic.rpt
decoder_dynamic
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 58 D TFFE + t 0 0 0 0 2 12 4 temp2 (:46)
- 50 D TFFE + t 0 0 0 0 1 12 5 temp1 (:47)
- 63 D TFFE + t 0 0 0 0 0 12 6 temp0 (:48)
- 55 D SOFT s t 1 0 1 5 3 1 0 ~546~1
(39) 36 C SOFT s t 1 0 1 5 3 1 0 ~570~1
(37) 35 C SOFT s t 1 0 1 5 3 1 0 ~594~1
- 42 C SOFT s t 1 0 1 5 3 1 0 ~618~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\kai\timer\decoder_dynamic.rpt
decoder_dynamic
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----- LC36 ~570~1
| +--- LC35 ~594~1
| | +- LC42 ~618~1
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'C'
LC | | | | A B C D | Logic cells that feed LAB 'C':
Pin
67 -> - - - | - - - - | <-- clk
23 -> - - * | - - * - | <-- h00
37 -> - * - | - - * - | <-- h01
20 -> * - - | - - * - | <-- h02
41 -> - - * | - - * - | <-- m00
42 -> - * - | - - * - | <-- m01
27 -> * - - | - - * - | <-- m02
28 -> - - * | - - * - | <-- s00
29 -> - * - | - - * - | <-- s01
30 -> * - - | - - * - | <-- s02
9 -> - - * | - - * - | <-- x00
10 -> - * - | - - * - | <-- x01
12 -> * - - | - - * - | <-- x02
14 -> - - * | - - * - | <-- x10
15 -> - * - | - - * - | <-- x11
17 -> * - - | - - * - | <-- x12
LC58 -> * * * | - - * * | <-- temp2
LC50 -> * * * | - - * * | <-- temp1
LC63 -> * * * | - - * * | <-- temp0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
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