decoder_dynamic.rpt
来自「利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。」· RPT 代码 · 共 655 行 · 第 1/2 页
RPT
655 行
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\kai\timer\decoder_dynamic.rpt
decoder_dynamic
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC53 q0
| +----------------------------- LC54 q1
| | +--------------------------- LC56 q2
| | | +------------------------- LC59 q3
| | | | +----------------------- LC60 sel0
| | | | | +--------------------- LC61 sel1
| | | | | | +------------------- LC62 sel2
| | | | | | | +----------------- LC64 sel3
| | | | | | | | +--------------- LC49 sel4
| | | | | | | | | +------------- LC52 sel5
| | | | | | | | | | +----------- LC57 sel6
| | | | | | | | | | | +--------- LC51 sel7
| | | | | | | | | | | | +------- LC58 temp2
| | | | | | | | | | | | | +----- LC50 temp1
| | | | | | | | | | | | | | +--- LC63 temp0
| | | | | | | | | | | | | | | +- LC55 ~546~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC58 -> * * * * * * * * * * * * * - - * | - - * * | <-- temp2
LC50 -> * * * * * * * * * * * * * * - * | - - * * | <-- temp1
LC63 -> * * * * * * * * * * * * * * * * | - - * * | <-- temp0
LC55 -> - - - * - - - - - - - - - - - - | - - - * | <-- ~546~1
Pin
67 -> - - - - - - - - - - - - - - - - | - - - - | <-- clk
22 -> - - - - - - - - - - - - - - - * | - - - * | <-- h03
25 -> * - - - - - - - - - - - - - - - | - - - * | <-- h10
19 -> - * - - - - - - - - - - - - - - | - - - * | <-- h11
36 -> - - * - - - - - - - - - - - - - | - - - * | <-- h12
40 -> - - - * - - - - - - - - - - - - | - - - * | <-- h13
47 -> - - - - - - - - - - - - - - - * | - - - * | <-- m03
46 -> * - - - - - - - - - - - - - - - | - - - * | <-- m10
50 -> - * - - - - - - - - - - - - - - | - - - * | <-- m11
33 -> - - * - - - - - - - - - - - - - | - - - * | <-- m12
24 -> - - - * - - - - - - - - - - - - | - - - * | <-- m13
32 -> - - - - - - - - - - - - - - - * | - - - * | <-- s03
4 -> * - - - - - - - - - - - - - - - | - - - * | <-- s10
5 -> - * - - - - - - - - - - - - - - | - - - * | <-- s11
7 -> - - * - - - - - - - - - - - - - | - - - * | <-- s12
8 -> - - - * - - - - - - - - - - - - | - - - * | <-- s13
13 -> - - - - - - - - - - - - - - - * | - - - * | <-- x03
18 -> - - - - - - - - - - - - - - - * | - - - * | <-- x13
LC36 -> - - * - - - - - - - - - - - - - | - - - * | <-- ~570~1
LC35 -> - * - - - - - - - - - - - - - - | - - - * | <-- ~594~1
LC42 -> * - - - - - - - - - - - - - - - | - - - * | <-- ~618~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\kai\timer\decoder_dynamic.rpt
decoder_dynamic
** EQUATIONS **
clk : INPUT;
h00 : INPUT;
h01 : INPUT;
h02 : INPUT;
h03 : INPUT;
h10 : INPUT;
h11 : INPUT;
h12 : INPUT;
h13 : INPUT;
m00 : INPUT;
m01 : INPUT;
m02 : INPUT;
m03 : INPUT;
m10 : INPUT;
m11 : INPUT;
m12 : INPUT;
m13 : INPUT;
s00 : INPUT;
s01 : INPUT;
s02 : INPUT;
s03 : INPUT;
s10 : INPUT;
s11 : INPUT;
s12 : INPUT;
s13 : INPUT;
x00 : INPUT;
x01 : INPUT;
x02 : INPUT;
x03 : INPUT;
x10 : INPUT;
x11 : INPUT;
x12 : INPUT;
x13 : INPUT;
-- Node name is 'q0'
-- Equation name is 'q0', location is LC053, type is output.
q0 = LCELL( _EQ001 $ VCC);
_EQ001 = !_LC042 & _X001 & _X002 & _X003;
_X001 = EXP( m10 & !temp0 & temp1 & !temp2);
_X002 = EXP( s10 & !temp0 & !temp1 & temp2);
_X003 = EXP( h10 & !temp0 & !temp1 & !temp2);
-- Node name is 'q1'
-- Equation name is 'q1', location is LC054, type is output.
q1 = LCELL( _EQ002 $ VCC);
_EQ002 = !_LC035 & _X004 & _X005 & _X006;
_X004 = EXP( m11 & !temp0 & temp1 & !temp2);
_X005 = EXP( s11 & !temp0 & !temp1 & temp2);
_X006 = EXP( h11 & !temp0 & !temp1 & !temp2);
-- Node name is 'q2'
-- Equation name is 'q2', location is LC056, type is output.
q2 = LCELL( _EQ003 $ VCC);
_EQ003 = !_LC036 & _X007 & _X008 & _X009;
_X007 = EXP( m12 & !temp0 & temp1 & !temp2);
_X008 = EXP( s12 & !temp0 & !temp1 & temp2);
_X009 = EXP( h12 & !temp0 & !temp1 & !temp2);
-- Node name is 'q3'
-- Equation name is 'q3', location is LC059, type is output.
q3 = LCELL( _EQ004 $ VCC);
_EQ004 = !_LC055 & _X010 & _X011 & _X012;
_X010 = EXP( m13 & !temp0 & temp1 & !temp2);
_X011 = EXP( s13 & !temp0 & !temp1 & temp2);
_X012 = EXP( h13 & !temp0 & !temp1 & !temp2);
-- Node name is 'sel0'
-- Equation name is 'sel0', location is LC060, type is output.
sel0 = LCELL( _EQ005 $ GND);
_EQ005 = temp0 & temp1 & temp2;
-- Node name is 'sel1'
-- Equation name is 'sel1', location is LC061, type is output.
sel1 = LCELL( _EQ006 $ GND);
_EQ006 = !temp0 & temp1 & temp2;
-- Node name is 'sel2'
-- Equation name is 'sel2', location is LC062, type is output.
sel2 = LCELL( _EQ007 $ GND);
_EQ007 = temp0 & !temp1 & temp2;
-- Node name is 'sel3'
-- Equation name is 'sel3', location is LC064, type is output.
sel3 = LCELL( _EQ008 $ GND);
_EQ008 = !temp0 & !temp1 & temp2;
-- Node name is 'sel4'
-- Equation name is 'sel4', location is LC049, type is output.
sel4 = LCELL( _EQ009 $ GND);
_EQ009 = temp0 & temp1 & !temp2;
-- Node name is 'sel5'
-- Equation name is 'sel5', location is LC052, type is output.
sel5 = LCELL( _EQ010 $ GND);
_EQ010 = !temp0 & temp1 & !temp2;
-- Node name is 'sel6'
-- Equation name is 'sel6', location is LC057, type is output.
sel6 = LCELL( _EQ011 $ GND);
_EQ011 = temp0 & !temp1 & !temp2;
-- Node name is 'sel7'
-- Equation name is 'sel7', location is LC051, type is output.
sel7 = LCELL( _EQ012 $ GND);
_EQ012 = !temp0 & !temp1 & !temp2;
-- Node name is ':48' = 'temp0'
-- Equation name is 'temp0', location is LC063, type is buried.
temp0 = TFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':47' = 'temp1'
-- Equation name is 'temp1', location is LC050, type is buried.
temp1 = TFFE( temp0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':46' = 'temp2'
-- Equation name is 'temp2', location is LC058, type is buried.
temp2 = TFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = temp0 & temp1;
-- Node name is '~546~1'
-- Equation name is '~546~1', location is LC055, type is buried.
-- synthesized logic cell
_LC055 = LCELL( _EQ014 $ GND);
_EQ014 = temp0 & temp1 & temp2 & x03
# m03 & temp0 & temp1 & !temp2
# s03 & temp0 & !temp1 & temp2
# !temp0 & temp1 & temp2 & x13
# h03 & temp0 & !temp1 & !temp2;
-- Node name is '~570~1'
-- Equation name is '~570~1', location is LC036, type is buried.
-- synthesized logic cell
_LC036 = LCELL( _EQ015 $ GND);
_EQ015 = temp0 & temp1 & temp2 & x02
# m02 & temp0 & temp1 & !temp2
# s02 & temp0 & !temp1 & temp2
# !temp0 & temp1 & temp2 & x12
# h02 & temp0 & !temp1 & !temp2;
-- Node name is '~594~1'
-- Equation name is '~594~1', location is LC035, type is buried.
-- synthesized logic cell
_LC035 = LCELL( _EQ016 $ GND);
_EQ016 = temp0 & temp1 & temp2 & x01
# m01 & temp0 & temp1 & !temp2
# s01 & temp0 & !temp1 & temp2
# !temp0 & temp1 & temp2 & x11
# h01 & temp0 & !temp1 & !temp2;
-- Node name is '~618~1'
-- Equation name is '~618~1', location is LC042, type is buried.
-- synthesized logic cell
_LC042 = LCELL( _EQ017 $ GND);
_EQ017 = temp0 & temp1 & temp2 & x00
# m00 & temp0 & temp1 & !temp2
# s00 & temp0 & !temp1 & temp2
# !temp0 & temp1 & temp2 & x10
# h00 & temp0 & !temp1 & !temp2;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\kai\timer\decoder_dynamic.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 6,449K
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