timer.tan.qmsg

来自「利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。」· QMSG 代码 · 共 11 行 · 第 1/5 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "timer.gdf" "" { Schematic "F:/eda/timer/timer.gdf" { { 64 0 168 80 "clk" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "59 " "Warning: Found 59 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "contr:26\|clkmm " "Info: Detected ripple clock \"contr:26\|clkmm\" as buffer" {  } { { "contr.vhd" "" { Text "F:/eda/timer/contr.vhd" 6 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "contr:26\|clkmm" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "contr:26\|clkh " "Info: Detected ripple clock \"contr:26\|clkh\" as buffer" {  } { { "contr.vhd" "" { Text "F:/eda/timer/contr.vhd" 6 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "contr:26\|clkh" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "contr:26\|clks " "Info: Detected ripple clock \"contr:26\|clks\" as buffer" {  } { { "contr.vhd" "" { Text "F:/eda/timer/contr.vhd" 6 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "contr:26\|clks" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "contr:26\|clkm " "Info: Detected ripple clock \"contr:26\|clkm\" as buffer" {  } { { "contr.vhd" "" { Text "F:/eda/timer/contr.vhd" 6 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "contr:26\|clkm" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "d_ff:18\|q2 " "Info: Detected ripple clock \"d_ff:18\|q2\" as buffer" {  } { { "d_ff.vhd" "" { Text "F:/eda/timer/d_ff.vhd" 6 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "d_ff:18\|q2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "decoder_dynamic:13\|Mux0~64 " "Info: Detected gated clock \"decoder_dynamic:13\|Mux0~64\" as buffer" {  } { { "decoder_dynamic.vhd" "" { Text "F:/eda/timer/decoder_dynamic.vhd" 24 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "decoder_dynamic:13\|Mux0~64" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "decoder_dynamic:13\|Mux0~63 " "Info: Detected gated clock \"decoder_dynamic:13\|Mux0~63\" as buffer" {  } { { "decoder_dynamic.vhd" "" { Text "F:/eda/timer/decoder_dynamic.vhd" 24 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "decoder_dynamic:13\|Mux0~63" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "mms:6\|shi\[3\] " "Info: Detected ripple clock \"mms:6\|shi\[3\]\" as buffer" {  } { { "mms.vhd" "" { Text "F:/eda/timer/mms.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "mms:6\|shi\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "decoder_dynamic:13\|Mux0~62 " "Info: Detected gated clock \"decoder_dynamic:13\|Mux0~62\" as buffer" {  } { { "decoder_dynamic.vhd" "" { Text "F:/eda/timer/decoder_dynamic.vhd" 24 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "decoder_dynamic:13\|Mux0~62" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "hour:17\|shi\[3\] " "Info: Detected ripple clock \"hour:17\|shi\[3\]\" as buffer" {  } { { "hour.vhd" "" { Text "F:/eda/timer/hour.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "hour:17\|shi\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "decoder_dynamic:13\|Mux0~61 " "Info: Detected gated clock \"decoder_dynamic:13\|Mux0~61\" as buffer" {  } { { "decoder_dynamic.vhd" "" { Text "F:/eda/timer/decoder_dynamic.vhd" 24 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "decoder_dynamic:13\|Mux0~61" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "decoder_dynamic:13\|Mux0~60 " "Info: Detected gated clock \"decoder_dynamic:13\|Mux0~60\" as buffer" {  } { { "decoder_dynamic.vhd" "" { Text "F:/eda/timer/decoder_dynamic.vhd" 24 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "decoder_dynamic:13\|Mux0~60" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "decoder_dynamic:13\|Mux1~59 " "Info: Detected gated clock \"decoder_dynamic:13\|Mux1~59\" as buffer" {  } { { "decoder_dynamic.vhd" "" { Text "F:/eda/timer/decoder_dynamic.vhd" 24 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "decoder_dynamic:13\|Mux1~59" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "mms:6\|shi\[2\] " "Info: Detected ripple clock \"mms:6\|shi\[2\]\" as buffer" {  } { { "mms.vhd" "" { Text "F:/eda/timer/mms.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "mms:6\|shi\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "decoder_dynamic:13\|Mux1~58 " "Info: Detected gated clock \"decoder_dynamic:13\|Mux1~58\" as buffer" {  } { { "decoder_dynamic.vhd" "" { Text "F:/eda/timer/decoder_dynamic.vhd" 24 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "decoder_dynamic:13\|Mux1~58" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "decoder_dynamic:13\|Mux1~57 " "Info: Detected gated clock \"decoder_dynamic:13\|Mux1~57\" as buffer" {  } { { "decoder_dynamic.vhd" "" { Text "F:/eda/timer/decoder_dynamic.vhd" 24 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "decoder_dynamic:13\|Mux1~57" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "hour:17\|shi\[2\] " "Info: Detected ripple clock \"hour:17\|shi\[2\]\" as buffer" {  } { { "hour.vhd" "" { Text "F:/eda/timer/hour.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "hour:17\|shi\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "sec:24\|shi\[3\] " "Info: Detected ripple clock \"sec:24\|shi\[3\]\" as buffer" {  } { { "sec.vhd" "" { Text "F:/eda/timer/sec.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sec:24\|shi\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "sec:24\|shi\[2\] " "Info: Detected ripple clock \"sec:24\|shi\[2\]\" as buffer" {  } { { "sec.vhd" "" { Text "F:/eda/timer/sec.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sec:24\|shi\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "sec:10\|shi\[3\] " "Info: Detected ripple clock \"sec:10\|shi\[3\]\" as buffer" {  } { { "sec.vhd" "" { Text "F:/eda/timer/sec.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sec:10\|shi\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "sec:10\|shi\[2\] " "Info: Detected ripple clock \"sec:10\|shi\[2\]\" as buffer" {  } { { "sec.vhd" "" { Text "F:/eda/timer/sec.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sec:10\|shi\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "decoder_dynamic:13\|Mux1~56 " "Info: Detected gated clock \"decoder_dynamic:13\|Mux1~56\" as buffer" {  } { { "decoder_dynamic.vhd" "" { Text "F:/eda/timer/decoder_dynamic.vhd" 24 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "decoder_dynamic:13\|Mux1~56" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "decoder_dynamic:13\|Mux1~55 " "Info: Detected gated clock \"decoder_dynamic:13\|Mux1~55\" as buffer" {  } { { "decoder_dynamic.vhd" "" { Text "F:/eda/timer/decoder_dynamic.vhd" 24 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "decoder_dynamic:13\|Mux1~55" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "decoder_dynamic:13\|Mux2~46 " "Info: Detected gated clock \"decoder_dynamic:13\|Mux2~46\" as buffer" {  } { { "decoder_dynamic.vhd" "" { Text "F:/eda/timer/decoder_dynamic.vhd" 24 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "decoder_dynamic:13\|Mux2~46" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "decoder_dynamic:13\|Mux2~45 " "Info: Detected gated clock \"decoder_dynamic:13\|Mux2~45\" as buffer" {  } { { "decoder_dynamic.vhd" "" { Text "F:/eda/timer/decoder_dynamic.vhd" 24 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "decoder_dynamic:13\|Mux2~45" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "mms:6\|shi\[1\] " "Info: Detected ripple clock \"mms:6\|shi\[1\]\" as buffer" {  } { { "mms.vhd" "" { Text "F:/eda/timer/mms.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "mms:6\|shi\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "decoder_dynamic:13\|Mux2~44 " "Info: Detected gated clock \"decoder_dynamic:13\|Mux2~44\" as buffer" {  } { { "decoder_dynamic.vhd" "" { Text "F:/eda/timer/decoder_dynamic.vhd" 24 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "decoder_dynamic:13\|Mux2~44" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "hour:17\|ge\[3\] " "Info: Detected ripple clock \"hour:17\|ge\[3\]\" as buffer" {  } { { "hour.vhd" "" { Text "F:/eda/timer/hour.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "hour:17\|ge\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "hour:17\|ge\[2\] " "Info: Detected ripple clock \"hour:17\|ge\[2\]\" as buffer" {  } { { "hour.vhd" "" { Text "F:/eda/timer/hour.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "hour:17\|ge\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "hour:17\|shi\[1\] " "Info: Detected ripple clock \"hour:17\|shi\[1\]\" as buffer" {  } { { "hour.vhd" "" { Text "F:/eda/timer/hour.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "hour:17\|shi\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "sec:24\|shi\[1\] " "Info: Detected ripple clock \"sec:24\|shi\[1\]\" as buffer" {  } { { "sec.vhd" "" { Text "F:/eda/timer/sec.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sec:24\|shi\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "sec:10\|shi\[1\] " "Info: Detected ripple clock \"sec:10\|shi\[1\]\" as buffer" {  } { { "sec.vhd" "" { Text "F:/eda/timer/sec.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sec:10\|shi\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "decoder_dynamic:13\|Mux2~43 " "Info: Detected gated clock \"decoder_dynamic:13\|Mux2~43\" as buffer" {  } { { "decoder_dynamic.vhd" "" { Text "F:/eda/timer/decoder_dynamic.vhd" 24 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "decoder_dynamic:13\|Mux2~43" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "mms:6\|ge\[2\] " "Info: Detected ripple clock \"mms:6\|ge\[2\]\" as buffer" {  } { { "mms.vhd" "" { Text "F:/eda/timer/mms.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "mms:6\|ge\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "mms:6\|ge\[3\] " "Info: Detected ripple clock \"mms:6\|ge\[3\]\" as buffer" {  } { { "mms.vhd" "" { Text "F:/eda/timer/mms.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "mms:6\|ge\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "mms:6\|ge\[1\] " "Info: Detected ripple clock \"mms:6\|ge\[1\]\" as buffer" {  } { { "mms.vhd" "" { Text "F:/eda/timer/mms.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "mms:6\|ge\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "decoder_dynamic:13\|Mux2~42 " "Info: Detected gated clock \"decoder_dynamic:13\|Mux2~42\" as buffer" {  } { { "decoder_dynamic.vhd" "" { Text "F:/eda/timer/decoder_dynamic.vhd" 24 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "decoder_dynamic:13\|Mux2~42" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "hour:17\|ge\[1\] " "Info: Detected ripple clock \"hour:17\|ge\[1\]\" as buffer" {  } { { "hour.vhd" "" { Text "F:/eda/timer/hour.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "hour:17\|ge\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "sec:10\|ge\[2\] " "Info: Detected ripple clock \"sec:10\|ge\[2\]\" as buffer" {  } { { "sec.vhd" "" { Text "F:/eda/timer/sec.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sec:10\|ge\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "sec:10\|ge\[3\] " "Info: Detected ripple clock \"sec:10\|ge\[3\]\" as buffer" {  } { { "sec.vhd" "" { Text "F:/eda/timer/sec.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sec:10\|ge\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "sec:10\|ge\[1\] " "Info: Detected ripple clock \"sec:10\|ge\[1\]\" as buffer" {  } { { "sec.vhd" "" { Text "F:/eda/timer/sec.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sec:10\|ge\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "sec:24\|ge\[3\] " "Info: Detected ripple clock \"sec:24\|ge\[3\]\" as buffer" {  } { { "sec.vhd" "" { Text "F:/eda/timer/sec.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sec:24\|ge\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "sec:24\|ge\[2\] " "Info: Detected ripple clock \"sec:24\|ge\[2\]\" as buffer" {  } { { "sec.vhd" "" { Text "F:/eda/timer/sec.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sec:24\|ge\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "sec:24\|ge\[1\] " "Info: Detected ripple clock \"sec:24\|ge\[1\]\" as buffer" {  } { { "sec.vhd" "" { Text "F:/eda/timer/sec.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sec:24\|ge\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "contr:26\|comb~1 " "Info: Detected gated clock \"contr:26\|comb~1\" as buffer" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "contr:26\|comb~1" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "contr:26\|comb~220 " "Info: Detected gated clock \"contr:26\|comb~220\" as buffer" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "contr:26\|comb~220" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "contr:26\|comb~218 " "Info: Detected gated clock \"contr:26\|comb~218\" as buffer" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "contr:26\|comb~218" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "contr:26\|tem\[0\] " "Info: Detected ripple clock \"contr:26\|tem\[0\]\" as buffer" {  } { { "contr.vhd" "" { Text "F:/eda/timer/contr.vhd" 14 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "contr:26\|tem\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "d_ff:18\|q1 " "Info: Detected ripple clock \"d_ff:18\|q1\" as buffer" {  } { { "d_ff.vhd" "" { Text "F:/eda/timer/d_ff.vhd" 6 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "d_ff:18\|q1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "contr:26\|tem\[2\] " "Info: Detected ripple clock \"contr:26\|tem\[2\]\" as buffer" {  } { { "contr.vhd" "" { Text "F:/eda/timer/contr.vhd" 14 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "contr:26\|tem\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "contr:26\|tem\[1\] " "Info: Detected ripple clock \"contr:26\|tem\[1\]\" as buffer" {  } { { "contr.vhd" "" { Text "F:/eda/timer/contr.vhd" 14 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "contr:26\|tem\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "contr:26\|comb~2 " "Info: Detected gated clock \"contr:26\|comb~2\" as buffer" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "contr:26\|comb~2" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "contr:26\|comb~219 " "Info: Detected gated clock \"contr:26\|comb~219\" as buffer" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "contr:26\|comb~219" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fre_20:5\|q " "Info: Detected ripple clock \"fre_20:5\|q\" as buffer" {  } { { "fre_20.vhd" "" { Text "F:/eda/timer/fre_20.vhd" 6 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fre_20:5\|q" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fre_100:8\|q " "Info: Detected ripple clock \"fre_100:8\|q\" as buffer" {  } { { "fre_100.vhd" "" { Text "F:/eda/timer/fre_100.vhd" 6 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fre_100:8\|q" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "decoder_dynamic:13\|temp\[1\] " "Info: Detected ripple clock \"decoder_dynamic:13\|temp\[1\]\" as buffer" {  } { { "decoder_dynamic.vhd" "" { Text "F:/eda/timer/decoder_dynamic.vhd" 15 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "decoder_dynamic:13\|temp\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "decoder_dynamic:13\|temp\[2\] " "Info: Detected ripple clock \"decoder_dynamic:13\|temp\[2\]\" as buffer" {  } { { "decoder_dynamic.vhd" "" { Text "F:/eda/timer/decoder_dynamic.vhd" 15 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "decoder_dynamic:13\|temp\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fre_100:4\|q " "Info: Detected ripple clock \"fre_100:4\|q\" as buffer" {  } { { "fre_100.vhd" "" { Text "F:/eda/timer/fre_100.vhd" 6 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fre_100:4\|q" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "decoder_dynamic:13\|temp\[0\] " "Info: Detected ripple clock \"decoder_dynamic:13\|temp\[0\]\" as buffer" {  } { { "decoder_dynamic.vhd" "" { Text "F:/eda/timer/decoder_dynamic.vhd" 15 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "decoder_dynamic:13\|temp\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register hour:17\|shi\[1\] register decoder:2\|q\[6\] 61.87 MHz 16.163 ns Internal " "Info: Clock \"clk\" has Internal fmax of 61.87 MHz between source register \"hour:17\|shi\[1\]\" and destination register \"decoder:2\|q\[6\]\" (period= 16.163 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.419 ns + Longest register register " "Info: + Longest register to register delay is 8.419 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns hour:17\|shi\[1\] 1 REG LC_X5_Y1_N2 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y1_N2; Fanout = 7; REG Node = 'hour:17\|shi\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { hour:17|shi[1] } "NODE_NAME" } } { "hour.vhd" "" { Text "F:/eda/timer/hour.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.067 ns) + CELL(0.511 ns) 2.578 ns decoder_dynamic:13\|Mux2~44 2 COMB LC_X6_Y3_N1 1 " "Info: 2: + IC(2.067 ns) + CELL(0.511 ns) = 2.578 ns; Loc. = LC_X6_Y3_N1; Fanout = 1; COMB Node = 'decoder_dynamic:13\|Mux2~44'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.578 ns" { hour:17|shi[1] decoder_dynamic:13|Mux2~44 } "NODE_NAME" } } { "decoder_dynamic.vhd" "" { Text "F:/eda/timer/decoder_dynamic.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.728 ns) + CELL(0.200 ns) 3.506 ns decoder_dynamic:13\|Mux2~45 3 COMB LC_X6_Y3_N0 1 " "Info: 3: + IC(0.728 ns) + CELL(0.200 ns) = 3.506 ns; Loc. = LC_X6_Y3_N0; Fanout = 1; COMB Node = 'decoder_dynamic:13\|Mux2~45'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.928 ns" { decoder_dynamic:13|Mux2~44 decoder_dynamic:13|Mux2~45 } "NODE_NAME" } } { "decoder_dynamic.vhd" "" { Text "F:/eda/timer/decoder_dynamic.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.794 ns) + CELL(0.511 ns) 4.811 ns decoder_dynamic:13\|Mux2~46 4 COMB LC_X6_Y3_N5 8 " "Info: 4: + IC(0.794 ns) + CELL(0.511 ns) = 4.811 ns; Loc. = LC_X6_Y3_N5; Fanout = 8; COMB Node = 'decoder_dynamic:13\|Mux2~46'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.305 ns" { decoder_dynamic:13|Mux2~45 decoder_dynamic:13|Mux2~46 } "NODE_NAME" } } { "decoder_dynamic.vhd" "" { Text "F:/eda/timer/decoder_dynamic.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.947 ns) + CELL(0.740 ns) 7.498 ns decoder:2\|Mux6~33 5 COMB LC_X5_Y4_N1 1 " "Info: 5: + IC(1.947 ns) + CELL(0.740 ns) = 7.498 ns; Loc. = LC_X5_Y4_N1; Fanout = 1; COMB Node = 'decoder:2\|Mux6~33'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.687 ns" { decoder_dynamic:13|Mux2~46 decoder:2|Mux6~33 } "NODE_NAME" } } { "decoder.vhd" "" { Text "F:/eda/timer/decoder.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.721 ns) + CELL(0.200 ns) 8.419 ns decoder:2\|q\[6\] 6 REG LC_X5_Y4_N4 1 " "Info: 6: + IC(0.721 ns) + CELL(0.200 ns) = 8.419 ns; Loc. = LC_X5_Y4_N4; Fanout = 1; REG Node = 'decoder:2\|q\[6\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.921 ns" { decoder:2|Mux6~33 decoder:2|q[6] } "NODE_NAME" } } { "decoder.vhd" "" { Text "F:/eda/timer/decoder.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.162 ns ( 25.68 % ) " "Info: Total cell delay = 2.162 ns ( 25.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.257 ns ( 74.32 % ) " "Info: Total interconnect delay = 6.257 ns ( 74.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.419 ns" { hour:17|shi[1] decoder_dynamic:13|Mux2~44 decoder_dynamic:13|Mux2~45 decoder_dynamic:13|Mux2~46 decoder:2|Mux6~33 decoder:2|q[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.419 ns" { hour:17|shi[1] decoder_dynamic:13|Mux2~44 decoder_dynamic:13|Mux2~45 decoder_dynamic:13|Mux2~46 decoder:2|Mux6~33 decoder:2|q[6] } { 0.000ns 2.067ns 0.728ns 0.794ns 1.947ns 0.721ns } { 0.000ns 0.511ns 0.200ns 0.511ns 0.740ns 0.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.244 ns - Smallest " "Info: - Smallest clock skew is -5.244 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 15.484 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 15.484 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 7 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 7; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "timer.gdf" "" { Schematic "F:/eda/timer/timer.gdf" { { 64 0 168 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns fre_100:8\|q 2 REG LC_X3_Y4_N9 8 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y4_N9; Fanout = 8; REG Node = 'fre_100:8\|q'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { clk fre_100:8|q } "NODE_NAME" } } { "fre_100.vhd" "" { Text "F:/eda/timer/fre_100.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.896 ns) + CELL(1.294 ns) 5.914 ns fre_100:4\|q 3 REG LC_X3_Y4_N0 9 " "Info: 3: + IC(0.896 ns) + CELL(1.294 ns) = 5.914 ns; Loc. = LC_X3_Y4_N0; Fanout = 9; REG Node = 'fre_100:4\|q'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.190 ns" { fre_100:8|q fre_100:4|q } "NODE_NAME" } } { "fre_100.vhd" "" { Text "F:/eda/timer/fre_100.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.987 ns) + CELL(1.294 ns) 9.195 ns decoder_dynamic:13\|temp\[0\] 4 REG LC_X7_Y4_N3 15 " "Info: 4: + IC(1.987 ns) + CELL(1.294 ns) = 9.195 ns; Loc. = LC_X7_Y4_N3; Fanout = 15; REG Node = 'decoder_dynamic:13\|temp\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.281 ns" { fre_100:4|q decoder_dynamic:13|temp[0] } "NODE_NAME" } } { "decoder_dynamic.vhd" "" { Text "F:/eda/timer/decoder_dynamic.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.131 ns) + CELL(0.740 ns) 12.066 ns decoder_dynamic:13\|Mux0~64 5 COMB LC_X6_Y2_N7 5 " "Info: 5: + IC(2.131 ns) + CELL(0.740 ns) = 12.066 ns; Loc. = LC_X6_Y2_N7; Fanout = 5; COMB Node = 'decoder_dynamic:13\|Mux0~64'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.871 ns" { decoder_dynamic:13|temp[0] decoder_dynamic:13|Mux0~64 } "NODE_NAME" } } { "decoder_dynamic.vhd" "" { Text "F:/eda/timer/decoder_dynamic.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.888 ns) + CELL(0.200 ns) 14.154 ns decoder:2\|Mux7~55 6 COMB LC_X5_Y4_N7 7 " "Info: 6: + IC(1.888 ns) + CELL(0.200 ns) = 14.154 ns; Loc. = LC_X5_Y4_N7; Fanout = 7; COMB Node = 'decoder:2\|Mux7~55'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.088 ns" { decoder_dynamic:13|Mux0~64 decoder:2|Mux7~55 } "NODE_NAME" } } { "decoder.vhd" "" { Text "F:/eda/timer/decoder.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.819 ns) + CELL(0.511 ns) 15.484 ns decoder:2\|q\[6\] 7 REG LC_X5_Y4_N4 1 " "Info: 7: + IC(0.819 ns) + CELL(0.511 ns) = 15.484 ns; Loc. = LC_X5_Y4_N4; Fanout = 1; REG Node = 'decoder:2\|q\[6\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.330 ns" { decoder:2|Mux7~55 decoder:2|q[6] } "NODE_NAME" } } { "decoder.vhd" "" { Text "F:/eda/timer/decoder.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.496 ns ( 41.95 % ) " "Info: Total cell delay = 6.496 ns ( 41.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.988 ns ( 58.05 % ) " "Info: Total interconnect delay = 8.988 ns ( 58.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.484 ns" { clk fre_100:8|q fre_100:4|q decoder_dynamic:13|temp[0] decoder_dynamic:13|Mux0~64 decoder:2|Mux7~55 decoder:2|q[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "15.484 ns" { clk clk~combout fre_100:8|q fre_100:4|q decoder_dynamic:13|temp[0] decoder_dynamic:13|Mux0~64 decoder:2|Mux7~55 decoder:2|q[6] } { 0.000ns 0.000ns 1.267ns 0.896ns 1.987ns 2.131ns 1.888ns 0.819ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.740ns 0.200ns 0.511ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 20.728 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 20.728 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 7 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 7; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "timer.gdf" "" { Schematic "F:/eda/timer/timer.gdf" { { 64 0 168 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns fre_100:8\|q 2 REG LC_X3_Y4_N9 8 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y4_N9; Fanout = 8; REG Node = 'fre_100:8\|q'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { clk fre_100:8|q } "NODE_NAME" } } { "fre_100.vhd" "" { Text "F:/eda/timer/fre_100.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.896 ns) + CELL(1.294 ns) 5.914 ns fre_100:4\|q 3 REG LC_X3_Y4_N0 9 " "Info: 3: + IC(0.896 ns) + CELL(1.294 ns) = 5.914 ns; Loc. = LC_X3_Y4_N0; Fanout = 9; REG Node = 'fre_100:4\|q'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.190 ns" { fre_100:8|q fre_100:4|q } "NODE_NAME" } } { "fre_100.vhd" "" { Text "F:/eda/timer/fre_100.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.045 ns) + CELL(1.294 ns) 9.253 ns fre_20:5\|q 4 REG LC_X2_Y3_N9 6 " "Info: 4: + IC(2.045 ns) + CELL(1.294 ns) = 9.253 ns; Loc. = LC_X2_Y3_N9; Fanout = 6; REG Node = 'fre_20:5\|q'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.339 ns" { fre_100:4|q fre_20:5|q } "NODE_NAME" } } { "fre_20.vhd" "" { Text "F:/eda/timer/fre_20.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.329 ns) + CELL(1.294 ns) 11.876 ns d_ff:18\|q2 5 REG LC_X3_Y3_N3 3 " "Info: 5: + IC(1.329 ns) + CELL(1.294 ns) = 11.876 ns; Loc. = LC_X3_Y3_N3; Fanout = 3; REG Node = 'd_ff:18\|q2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.623 ns" { fre_20:5|q d_ff:18|q2 } "NODE_NAME" } } { "d_ff.vhd" "" { Text "F:/eda/timer/d_ff.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(1.294 ns) 14.099 ns contr:26\|tem\[1\] 6 REG LC_X3_Y3_N6 15 " "Info: 6: + IC(0.929 ns) + CELL(1.294 ns) = 14.099 ns; Loc. = LC_X3_Y3_N6; Fanout = 15; REG Node = 'contr:26\|tem\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.223 ns" { d_ff:18|q2 contr:26|tem[1] } "NODE_NAME" } } { "contr.vhd" "" { Text "F:/eda/timer/contr.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.050 ns) + CELL(0.914 ns) 16.063 ns contr:26\|comb~220 7 COMB LC_X3_Y3_N5 1 " "Info: 7: + IC(1.050 ns) + CELL(0.914 ns) = 16.063 ns; Loc. = LC_X3_Y3_N5; Fanout = 1; COMB Node = 'contr:26\|comb~220'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.964 ns" { contr:26|tem[1] contr:26|comb~220 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(0.200 ns) 17.963 ns contr:26\|clkh 8 REG LC_X4_Y4_N0 8 " "Info: 8: + IC(1.700 ns) + CELL(0.200 ns) = 17.963 ns; Loc. = LC_X4_Y4_N0; Fanout = 8; REG Node = 'contr:26\|clkh'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { contr:26|comb~220 contr:26|clkh } "NODE_NAME" } } { "contr.vhd" "" { Text "F:/eda/timer/contr.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.847 ns) + CELL(0.918 ns) 20.728 ns hour:17\|shi\[1\] 9 REG LC_X5_Y1_N2 7 " "Info: 9: + IC(1.847 ns) + CELL(0.918 ns) = 20.728 ns; Loc. = LC_X5_Y1_N2; Fanout = 7; REG Node = 'hour:17\|shi\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.765 ns" { contr:26|clkh hour:17|shi[1] } "NODE_NAME" } } { "hour.vhd" "" { Text "F:/eda/timer/hour.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.665 ns ( 46.63 % ) " "Info: Total cell delay = 9.665 ns ( 46.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.063 ns ( 53.37 % ) " "Info: Total interconnect delay = 11.063 ns ( 53.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "20.728 ns" { clk fre_100:8|q fre_100:4|q fre_20:5|q d_ff:18|q2 contr:26|tem[1] contr:26|comb~220 contr:26|clkh hour:17|shi[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "20.728 ns" { clk clk~combout fre_100:8|q fre_100:4|q fre_20:5|q d_ff:18|q2 contr:26|tem[1] contr:26|comb~220 contr:26|clkh hour:17|shi[1] } { 0.000ns 0.000ns 1.267ns 0.896ns 2.045ns 1.329ns 0.929ns 1.050ns 1.700ns 1.847ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 1.294ns 1.294ns 0.914ns 0.200ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.484 ns" { clk fre_100:8|q fre_100:4|q decoder_dynamic:13|temp[0] decoder_dynamic:13|Mux0~64 decoder:2|Mux7~55 decoder:2|q[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "15.484 ns" { clk clk~combout fre_100:8|q fre_100:4|q decoder_dynamic:13|temp[0] decoder_dynamic:13|Mux0~64 decoder:2|Mux7~55 decoder:2|q[6] } { 0.000ns 0.000ns 1.267ns 0.896ns 1.987ns 2.131ns 1.888ns 0.819ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.740ns 0.200ns 0.511ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "20.728 ns" { clk fre_100:8|q fre_100:4|q fre_20:5|q d_ff:18|q2 contr:26|tem[1] contr:26|comb~220 contr:26|clkh hour:17|shi[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "20.728 ns" { clk clk~combout fre_100:8|q fre_100:4|q fre_20:5|q d_ff:18|q2 contr:26|tem[1] contr:26|comb~220 contr:26|clkh hour:17|shi[1] } { 0.000ns 0.000ns 1.267ns 0.896ns 2.045ns 1.329ns 0.929ns 1.050ns 1.700ns 1.847ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 1.294ns 1.294ns 0.914ns 0.200ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "hour.vhd" "" { Text "F:/eda/timer/hour.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.124 ns + " "Info: + Micro setup delay of destination is 2.124 ns" {  } { { "decoder.vhd" "" { Text "F:/eda/timer/decoder.vhd" 10 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.419 ns" { hour:17|shi[1] decoder_dynamic:13|Mux2~44 decoder_dynamic:13|Mux2~45 decoder_dynamic:13|Mux2~46 decoder:2|Mux6~33 decoder:2|q[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.419 ns" { hour:17|shi[1] decoder_dynamic:13|Mux2~44 decoder_dynamic:13|Mux2~45 decoder_dynamic:13|Mux2~46 decoder:2|Mux6~33 decoder:2|q[6] } { 0.000ns 2.067ns 0.728ns 0.794ns 1.947ns 0.721ns } { 0.000ns 0.511ns 0.200ns 0.511ns 0.740ns 0.200ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.484 ns" { clk fre_100:8|q fre_100:4|q decoder_dynamic:13|temp[0] decoder_dynamic:13|Mux0~64 decoder:2|Mux7~55 decoder:2|q[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "15.484 ns" { clk clk~combout fre_100:8|q fre_100:4|q decoder_dynamic:13|temp[0] decoder_dynamic:13|Mux0~64 decoder:2|Mux7~55 decoder:2|q[6] } { 0.000ns 0.000ns 1.267ns 0.896ns 1.987ns 2.131ns 1.888ns 0.819ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.740ns 0.200ns 0.511ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "20.728 ns" { clk fre_100:8|q fre_100:4|q fre_20:5|q d_ff:18|q2 contr:26|tem[1] contr:26|comb~220 contr:26|clkh hour:17|shi[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "20.728 ns" { clk clk~combout fre_100:8|q fre_100:4|q fre_20:5|q d_ff:18|q2 contr:26|tem[1] contr:26|comb~220 contr:26|clkh hour:17|shi[1] } { 0.000ns 0.000ns 1.267ns 0.896ns 2.045ns 1.329ns 0.929ns 1.050ns 1.700ns 1.847ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 1.294ns 1.294ns 0.914ns 0.200ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}